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    Combined digital-to-analog converter and signal filter
    2.
    发明专利
    Combined digital-to-analog converter and signal filter 审中-公开
    组合数字到模拟转换器和信号滤波器

    公开(公告)号：JP2011172234A

    公开(公告)日：2011-09-01

    申请号：JP2011051947

    申请日：2011-03-09

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： BURKE JOSEPH PATRICK

    IPC: H03M1/66 ,  H03M1/06 ,  H03M3/00 ,  H04B1/69

    CPC classification number: H03M1/0626 ,  H03M1/66 ,  H03M3/504 ,  H04B1/71635

    Abstract: PROBLEM TO BE SOLVED: To provide a wide-band low-pass filter that has a simple structure and ensures low cost and ease of design. SOLUTION: An electronic circuit that processes a digital signal includes: a plurality of digital delay circuits, each of which generates a replica whose digital signal is delayed; a plurality of digital-to-analog converters each of which converts the digital signal or the delayed replica from one of the delay circuits into an analog signal; a plurality of analog gain circuits each of which adjusts the analog signal from the digital-to-analog converter in accordance with a gain factor and each of which has an output; and an analog adder which adds the output from the analog gain circuit. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供具有简单结构并且确保低成本和易于设计的宽带低通滤波器。 解决方案：处理数字信号的电子电路包括：多个数字延迟电路，每个数字延迟电路产生其数字信号被延迟的副本; 多个数模转换器，每个转换器将数字信号或延迟复制品从延迟电路之一转换为模拟信号; 多个模拟增益电路，每个模拟增益电路根据增益因子调整来自数模转换器的模拟信号，并且每个模拟增益电路具有输出; 以及将模拟增益电路的输出相加的模拟加法器。 版权所有（C）2011，JPO＆INPIT

    Jtag power collapse debug
    3.
    发明专利
    Jtag power collapse debug 有权
    JTAG电源调试

    公开(公告)号：JP2013047964A

    公开(公告)日：2013-03-07

    申请号：JP2012223429

    申请日：2012-10-05

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： MATTHEW LEVI SEVERSON ,  BURKE JOSEPH PATRICK ,  PHILIP POTTIER

    IPC: G06F11/28

    CPC classification number: G06F11/3656

    Abstract: PROBLEM TO BE SOLVED: To execute a debug operation on a processor after a power collapse.SOLUTION: Status registers of a processor are scanned by using a debugger. When a clock edge of a reference clock fails to appear on the pin of a re-synchronized timing clock RTCK of a JTAG interface in a certain period, a timeout condition is detected. The debugger enters a debug logical reset state. The debugger detects a next RTCK edge indicating that the processor has become active again. The debugger scans the status registers, and determines the current state of the processor. When the debugger determining that the processor was halted due to a power collapse, the debugger restores debug registers, ETM registers, ETB registers, or their arbitrary combination typically within 4 milliseconds. The debugger restarts the processor once the registers are restored.

    Abstract translation: 要解决的问题：在电源崩溃后对处理器执行调试操作。 解决方案：使用调试器扫描处理器的状态寄存器。 当某个时间段内的参考时钟的时钟沿不能出现在JTAG接口的同步定时时钟RTCK的引脚上时，检测到超时状态。 调试器进入调试逻辑复位状态。 调试器检测下一个RTCK边沿，指示处理器已经再次变为活动状态。 调试器扫描状态寄存器，并确定处理器的当前状态。 当调试器确定处理器由于电源崩溃而停止时，调试器通常在4毫秒内恢复调试寄存器，ETM寄存器，ETB寄存器或其任意组合。 调试器在恢复寄存器后重新启动处理器。 版权所有（C）2013，JPO＆INPIT

    Combined digital-to-analog converter and signal filter
    4.
    发明专利
    Combined digital-to-analog converter and signal filter 审中-公开
    组合数字到模拟转换器和信号滤波器

    公开(公告)号：JP2013085256A

    公开(公告)日：2013-05-09

    申请号：JP2012243911

    申请日：2012-11-05

    Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

    Inventor： BURKE JOSEPH PATRICK

    IPC: H03M1/66 ,  H03M1/06 ,  H03M3/00 ,  H04B1/69

    CPC classification number: H03M1/0626 ,  H03M1/66 ,  H03M3/504 ,  H04B1/71635

    Abstract: PROBLEM TO BE SOLVED: To provide an analog low-pass filter which may be used in a variety of applications and in ultrawide band applications.SOLUTION: An electronic circuit for processing a digital signal 201 includes a plurality of digital delay circuits 203, 205, 207, each configured to produce a delayed replica of the digital signal; a plurality of digital-to-analog converters 211, 213, 215, 217, each configured to convert the digital signal or the delayed replica from one of the delay circuits into an analog signal; a plurality of analog gain circuits 221, 223, 225, 227, each configured to adjust the analog signal from the digital-to-analog converters by a gain factor and each having an output; and an analog summer 231 configured to sum the outputs of the analog gain circuits.

    Abstract translation: 要解决的问题：提供可用于各种应用和超宽带应用中的模拟低通滤波器。 解决方案：用于处理数字信号201的电子电路包括多个数字延迟电路203,205,207，每个数字延迟电路被配置为产生数字信号的延迟复制品; 多个数模转换器211,213,215,217，每个被配置为将数字信号或延迟的副本从一个延迟电路转换为模拟信号; 多个模拟增益电路221,223,225,227，其被配置为通过增益因子调整来自数模转换器的模拟信号，并且每个具有输出; 以及被配置为对模拟增益电路的输出求和的模拟加法器231。 版权所有（C）2013，JPO＆INPIT

    Over the air acquisition of radio frequency impairment information
    7.
    发明专利
    Over the air acquisition of radio frequency impairment information 未知

    公开(公告)号：AU2017281246A1

    公开(公告)日：2018-12-06

    申请号：AU2017281246

    申请日：2017-05-19

    Applicant: QUALCOMM INC

    Inventor： WEISSMAN HAIM MENDEL ,  GUTMAN IGOR ,  BURKE JOSEPH PATRICK ,  CHELLAPPA VIJAY ,  VERMA SUMIT ,  DRAXLER PAUL

    IPC: H04B17/309 ,  H04B17/354 ,  H04B17/373 ,  H04L27/38

    Abstract: Systems and methods for providing indications about the TX RF non-linear impairments are disclosed. In accordance with some implementations, a first device (UE or base station) estimates EVM indications for the signal and determines if the EVM indications is above a threshold. The first device may transmit the estimated TX non-linearity indications such as AM-AM, AM-PM, Volterra coefficients, and/or other performance metrics to a second device, that transmitted the signal, when it is determined that the EVM indications is above the threshold. Systems and methods for wireless communication impairment correction are also disclosed wherein, in accordance with some implementations, a first device receives estimated TX non-linearity indications such as AM-AM, AM-PM, and/or Volterra coefficients from a second device and performs non-linear correction of a transmit signal for the second receiver device based at least in part on the EVM indications. Other aspects, embodiments, and features are also claimed and described.

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