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公开(公告)号：HK1033718A1
公开(公告)日：2001-09-14
申请号：HK01103050
申请日：2001-04-27
Applicant: QUALCOMM INC
Inventor： CICCARELLI STEVEN C , YOUNIS SAED G
IPC: G01S19/07 , G01S19/11 , G01S19/12 , G01S19/31 , H04B1/26 , H04B1/38 , H04B1/40 , H04B1/62 , H04L27/22 , H04B
Abstract: A receiver that downconverts input signals modulated using first, second, third and fourth modulation formats to a common intermediate frequency range. The first and second modulation formats are transmitted to the receiver in a first frequency range, the third modulation format is transmitted to the receiver in a second frequency range, and the fourth modulation format is transmitted to the receiver in a third frequency range. The input signals are provided to first, second and third band selection filters that respectively select first, second and third frequency ranges. A first downconverter is coupled to an output of the first band selection filter, and downconverts signals from the first frequency range to the common intermediate frequency range. A second downconverter is selectively coupled by a switch to either an output of the second band selection filter or an output of the third band selection filter, and downconverts signals from either the second frequency range or the third frequency range to the common intermediate frequency range. The second downconverter has an input coupled to a frequency doubling circuit. Switching circuitry selectively couples one of either a first oscillating signal from a voltage controlled oscillator (VCO) having a VCO frequency range or a second oscillating signal at a second frequency that is outside the VCO frequency range to an input of the first downconverter and an input of the frequency doubling circuit.
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公开(公告)号：ZA988204B
公开(公告)日：2000-07-07
申请号：ZA988204
申请日：1998-09-08
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH S , YOUNIS SAED G
Abstract: A bandpass SIGMA DELTA DC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, or a two-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a SIGMA DELTA ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 SIGMA DELTA ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass SIGMA DELTA ADC can also be used in conjunction with undersampling to provide a frequency downconversion.
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公开(公告)号：CA2354623A1
公开(公告)日：2000-06-22
申请号：CA2354623
申请日：1999-12-14
Applicant: QUALCOMM INC
Inventor： YOUNIS SAED G , BUTTERFIELD DANIEL KEYES
IPC: H03M3/02
Abstract: An inventive high-resolution Delta-Sigma analog-to-digital converter (15) using a Continuous-Time implementation having suppressed sensitivity to cloc k jitter. The inventive method and apparatus suppresses the sensitivity to jitter by the square of the oversampling ratio when compared to current Continuous-Time implementations of Delta-Sigma modulators. The present invention preferably includes a digital-to-analog converter (17) that ensure s that the integral of an output voltage is constant over a clock duty cycle regardless of clock jitter. The digital-to-analog converter (17) preferably includes at least two switches and a capacitor (28).
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公开(公告)号：NO20002931D0
公开(公告)日：2000-06-08
申请号：NO20002931
申请日：2000-06-08
Applicant: QUALCOMM INC
Inventor： CICCARELLI STEVEN C , YOUNIS SAED G , KAUFMAN RALPH E
Abstract: A programmable linear receiver which provides the requisite level of system performance at reduced power consumption. The receiver minimizes power consumption based on measurement of the non-linearity in the output signal from the receiver. The amount of non-linearity can be measured by the RSSI slope or energy-per-chip-to-noise-ratio (Ec/Io) measurement. The RSSI slope is the ratio of the change in the output signal plus intermodulation to the change in the input signal. The input signal level is periodically increased by a predetermined level and the output signal from the receiver is measured. The output signal comprises the desired signal and intermodulation products from non-linearity within the receiver. When the receiver is operating linearly, the output signal level increases dB per dB with the input signal level. However, as the receiver transitions into non-linear region, intermodulation products due to non-linearity increase faster than the desired signal. By detecting the RSSI slope, the amount of degradation due to non-linearity can be determined. This information is then used to adjust the IIP3 operating point of the amplifiers and mixer to provide the requisite level of performance while minimizing power consumption.
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公开(公告)号：AU1717899A
公开(公告)日：1999-06-28
申请号：AU1717899
申请日：1998-12-08
Applicant: QUALCOMM INC
Inventor： BAZARJANI SEYFOLLAH S , CICCARELLI STEVEN C , YOUNIS SAED G , BUTTERFIELD DANIEL K
Abstract: A receiver comprising a sigma-delta analog-to-digital converter ( SIGMA DELTA ADC) can be utilized in one of four configurations, as a subsampling bandpass receiver, a subsampling baseband receiver, a Nyquist sampling bandpass receiver, or a Nyquist sampling baseband receiver. For subsampling SIGMA DELTA receivers, the sampling frequency is less than twice the center frequency of the input signal into the SIGMA DELTA ADC. For Nyquist sampling SIGMA DELTA receivers, the sampling frequency is at least twice the highest frequency of the input signal into the SIGMA DELTA ADC. For baseband SIGMA DELTA receivers, the center frequency of the output signal from the SIGMA DELTA ADC is approximately zero or DC. For bandpass SIGMA DELTA receivers, the center frequency of the output signal from the SIGMA DELTA ADC is greater than zero. The sampling frequency can be selected based on the bandwidth of the input signal to simplify the design of the digital circuits used to process the output samples from the SIGMA DELTA ADC. Furthermore, the center frequency of the input signal can be selected based on the sampling frequency and the bandwidth of the input signal. The SIGMA DELTA ADC within the receiver provides many benefits.
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Patent Agency Ranking
公开(公告)号：AU1632999A
公开(公告)日：1999-06-28
申请号：AU1632999
申请日：1998-12-08
Applicant: QUALCOMM INC
Inventor： CICCARELLI STEVEN C , YOUNIS SAED G , KAUFMAN RALPH E
Abstract: A programmable linear receiver which provides the requisite level of system performance at reduced power consumption. The receiver minimizes power consumption based on measurement of the non-linearity in the output signal from the receiver. The amount of non-linearity can be measured by the RSSI slope or energy-per-chip-to-noise-ratio (Ec/Io) measurement. The RSSI slope is the ratio of the change in the output signal plus intermodulation to the change in the input signal. The input signal level is periodically increased by a predetermined level and the output signal from the receiver is measured. The output signal comprises the desired signal and intermodulation products from non-linearity within the receiver. When the receiver is operating linearly, the output signal level increases dB per dB with the input signal level. However, as the receiver transitions into non-linear region, intermodulation products due to non-linearity increase faster than the desired signal. By detecting the RSSI slope, the amount of degradation due to non-linearity can be determined. This information is then used to adjust the IIP3 operating point of the amplifiers and mixer to provide the requisite level of performance while minimizing power consumption.
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公开(公告)号：AU2010214743A1
公开(公告)日：2010-09-23
申请号：AU2010214743
申请日：2010-08-31
Applicant: QUALCOMM INC
Inventor： KAUFMAN RALPH , ZHANG HAITAO , YOUNIS SAED G , WILBORN THOMAS , FILIPOVIC DANIEL , LIN JIAN , SIMIC EMILIJA
Abstract: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.
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公开(公告)号：AU2008200624A1
公开(公告)日：2008-03-06
申请号：AU2008200624
申请日：2008-02-08
Applicant: QUALCOMM INC
Inventor： FILIPOVIC DANIEL , KAUFMAN RALPH , YOUNIS SAED G , WILBORN THOMAS , LIN JIAN , ZHANG HAITAO , SIMIC EMILIJA
Abstract: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.
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公开(公告)号：HK1068470A1
公开(公告)日：2005-04-29
申请号：HK05100669
申请日：2001-06-22
Applicant: QUALCOMM INC
Inventor： STEVEN CICCARELLI , YOUNIS SAED G
IPC: H04B20060101 , G01S19/07 , G01S19/11 , G01S19/12 , G01S19/31 , H04B1/26 , H04B1/38 , H04B1/40 , H04B1/62 , H04L27/22
Abstract: A receiver that downconverts input signals modulated using first, second, third and fourth modulation formats to a common intermediate frequency range. The first and second modulation formats are transmitted to the receiver in a first frequency range, the third modulation format is transmitted to the receiver in a second frequency range, and the fourth modulation format is transmitted to the receiver in a third frequency range. The input signals are provided to first, second and third band selection filters that respectively select first, second and third frequency ranges. A first downconverter is coupled to an output of the first band selection filter, and downconverts signals from the first frequency range to the common intermediate frequency range. A second downconverter is selectively coupled by a switch to either an output of the second band selection filter or an output of the third band selection filter, and downconverts signals from either the second frequency range or the third frequency range to the common intermediate frequency range. The second downconverter has an input coupled to a frequency doubling circuit. Switching circuitry selectively couples one of either a first oscillating signal from a voltage controlled oscillator (VCO) having a VCO frequency range or a second oscillating signal at a second frequency that is outside the VCO frequency range to an input of the first downconverter and an input of the frequency doubling circuit.
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公开(公告)号：BR0208145A
公开(公告)日：2004-08-24
申请号：BR0208145
申请日：2002-03-11
Applicant: QUALCOMM INC
Inventor： YOUNIS SAED G
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