公开(公告)号：EP2780941A1

公开(公告)日：2014-09-24

申请号：EP12805818.7

申请日：2012-11-15

Applicant: Qualcomm Incorporated

Inventor： HADJICHRISTOS, Aristotele ,  SAHOTA, Gurkanwal Singh ,  CICCARELLI, Steven C. ,  WILDING, David J. ,  LANE, Ryan D. ,  HOLENSTEIN, Christian ,  SHAH, Milind P.

IPC: H01L23/66 ,  H01L25/16

CPC classification number: H05K3/368 ,  H01L23/66 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15321 ,  H04B1/40 ,  H05K13/0465 ,  Y10T29/49126 ,  Y10T29/5317 ,  H01L2924/00

Abstract: A radio frequency package on package (PoP) circuit is described. The radio frequency package on package (PoP) circuit includes a first radio frequency package (306). The first radio frequency package includes radio frequency components (310, 312, 314, 316). The radio frequency package on package (PoP) circuit also includes a second radio frequency package (308). The second radio frequency package includes radio frequency components (322, 324). The first radio frequency package and the second radio frequency package are in a vertical configuration. The radio frequency components on the first radio frequency package are designed to reduce the effects of ground inductance.

公开(公告)号：EP2319175A2

公开(公告)日：2011-05-11

申请号：EP09791101.0

申请日：2009-08-03

Applicant: QUALCOMM Incorporated

Inventor： TASIC, Aleksandar ,  HOLENSTEIN, Christian ,  DENG, Junxiong

IPC: H03G3/30

CPC classification number: H03G3/3052

Abstract: A circuit is described. The circuit includes a low noise amplifier (LNA), a passive switching core (PSC), a transimpedance amplifier filter (TIA-filter) and a degenerative-impedance gain-tuning network (Zdeg network) having a first Zdeg network input lead, a second Zdeg network input lead, a first Zdeg network output lead and a second Zdeg network output lead, wherein the first Zdeg network input lead is coupled to a first output lead of the LNA and the second Zdeg network input lead is coupled to a second output lead of the LNA, and wherein the first Zdeg network output lead is coupled to a first signal input lead of the PSC and the second Zdeg network output lead is coupled to a second signal input lead of the PSC. The LNA, the Zdeg network, the PSC, and the TIA-filter together form a receiver. A receiver gain is adjusted by the Zdeg network.

公开(公告)号：EP2248256A1

公开(公告)日：2010-11-10

申请号：EP09708122.8

申请日：2009-02-06

Applicant: QUALCOMM Incorporated

Inventor： HOLENSTEIN, Christian ,  DENG, Junxiong ,  KIM, Namsoo

IPC: H03F3/45 ,  H03F3/193 ,  H03F1/32 ,  H03G1/00

CPC classification number: H03F3/193 ,  H03F1/3205 ,  H03F1/3211 ,  H03F3/45188 ,  H03F2200/294 ,  H03F2200/357 ,  H03F2200/451 ,  H03F2203/45246 ,  H03F2203/45318 ,  H03F2203/45386 ,  H03F2203/45396 ,  H03G1/0029

Abstract: A differential low noise amplifier (LNA) is operable in a selectable one of two modes. The LNA includes a first transistor (204), a second transistor (205), a third transistor (206) and a fourth transistor. In the first mode (PDC mode), the four transistors are configured to operate as a post-distortion cancellation (PDC) LNA. The third (206) and fourth (207) transistors operate as cancel transistors that improve linearity, but reduce LNA gain somewhat. In the second mode (high gain mode), the third (206) and fourth (207) transistors are configured so that amplified versions of the LNA input signal that they output are added to amplified versions of the LNA input signal that are output by the first and second main transistors (204, 205), resulting in increased gain. Multiplexing circuits are provided within the LNA so that the LNA is configurable into a selectable one of the two modes by controlling a digital mode control signal supplied to the LNA.

公开(公告)号：EP1402631A2

公开(公告)日：2004-03-31

申请号：EP02709570.2

申请日：2002-02-15

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Tao ,  HOLENSTEIN, Christian ,  KANG, Injup ,  WALKER, Brett, C. ,  PETERZELL, Paul, E. ,  CHALLA, Raghu ,  SEVERSON, Matthew, L.

IPC: H03G3/30 ,  H03D3/00 ,  H04B1/40

CPC classification number: H03G3/3078 ,  H03G3/3068 ,  H03G3/3089

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.