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    DEVICES AND METHODS FOR REDUCING NOISE IN DIGITALLY CONTROLLED OSCILLATORS
    43.
    发明公开
    DEVICES AND METHODS FOR REDUCING NOISE IN DIGITALLY CONTROLLED OSCILLATORS 审中-公开
    器件和方法中的噪声数字控制振荡器还原

    公开(公告)号：EP3020133A1

    公开(公告)日：2016-05-18

    申请号：EP14747193.2

    申请日：2014-07-07

    Applicant: Qualcomm Incorporated

    Inventor： BALLANTYNE, Gary, John ,  SUN, Bo ,  TANG, Yi ,  YANG, Zixiang ,  ENSAFDARAN, Masoud

    IPC: H03L7/099

    CPC classification number: H03L7/0991 ,  H03B5/1265 ,  H03B2200/0088 ,  H03B2201/025 ,  H03B2202/017 ,  H03J5/24 ,  H03J2200/10 ,  H03J2200/36 ,  H03L7/099 ,  H03L2207/50

    Abstract: One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary.

    Abstract translation: 一个特征涉及一种数字控制振荡器（DCO）做包括一可变电容器和噪声降低电路。 可变电容器具有可变电容值做了DCO的输出频率的控制。 可变电容值是基于由第一电容器组，由第二电容器组提供的第二银行电容值，并通过在辅助电容器组提供辅助银行电容值提供第一组电容值。降噪电路是angepasst 通过调整辅助银行电容值，同时保持所述第一银行电容值中的至少一个和/或所述第二隔堤电容值基本不变，以调整可变电容值。 之前调节可变电容值，降噪电路可以确定性矿做跨电容器组敏感边界的接收到的输入DCO控制字转换。

    MIXED SIGNAL TDC WITH EMBEDDED T2V ADC
    44.
    发明公开
    MIXED SIGNAL TDC WITH EMBEDDED T2V ADC 审中-公开
    具有混合信号和嵌入式T2V模拟数字转换器时间数字转换器

    公开(公告)号：EP2972598A2

    公开(公告)日：2016-01-20

    申请号：EP14714891.0

    申请日：2014-03-12

    Applicant: Qualcomm Incorporated

    Inventor： TANG, Yi ,  SUN, Bo

    IPC: G04F10/00 ,  H03L7/08

    Abstract: A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.

    SYSTEM AND METHOD FOR BIASING ACTIVE DEVICES
    47.
    发明公开
    SYSTEM AND METHOD FOR BIASING ACTIVE DEVICES 审中-公开
    系统VERFAHREN ZUR VORMAGNETISIERUNG AKTIVER VORRICHTUNGEN

    公开(公告)号：EP2510414A1

    公开(公告)日：2012-10-17

    申请号：EP10796534.5

    申请日：2010-12-10

    Applicant: Qualcomm Incorporated

    Inventor： SUN, Bo

    IPC: G05F1/46 ,  H03M1/80 ,  H03G3/30

    CPC classification number: G05F1/46 ,  H03F1/0261 ,  H03F1/223 ,  H03F3/195 ,  H03F2200/108 ,  H03F2200/27 ,  H03F2200/294 ,  H03F2200/321 ,  H04B2001/6908

    Abstract: An apparatus for generating a bias voltage for an active device is disclosed, comprising a first voltage source, a capacitive element adapted to generate a charge in response to the first voltage source, and a first switching element adapted to deliver the charge to generate the bias voltage for the active device. The apparatus may comprise a controller adapted to control a capacitive element based on one or more characteristics of the active device. Alternatively, the controller may also control the capacitance of the capacitive element based on a reference voltage that is, in turn, based on one or more characteristics of the active device. The apparatus may also comprise a second voltage source adapted to generate a second voltage from which the bias voltage may be generated. The second voltage may be based on one or more characteristics of the active device. The apparatus may comprise a second switching element adapted to selectively enable and disable the active device.

    Abstract translation: 公开了一种用于产生用于有源器件的偏置电压的装置，包括第一电压源，适于响应于第一电压源产生电荷的电容元件，以及适于传送电荷以产生偏置的第一开关元件 有源器件的电压。 该装置可以包括适于基于有源器件的一个或多个特性来控制电容元件的控制器。 或者，控制器还可以基于参考电压来控制电容元件的电容，参考电压又是基于有源器件的一个或多个特性。 该装置还可以包括适于产生可产生偏置电压的第二电压的第二电压源。 第二电压可以基于有源器件的一个或多个特性。 该装置可以包括适于选择性地启用和禁用有源装置的第二开关元件。

    SYSTEM AND METHOD OF CALIBRATING POWER-ON GATING WINDOW FOR A TIME-TO-DIGITAL CONVERTER (TDC) OF A DIGITAL PHASE LOCKED LOOP (DPLL)
    48.
    发明公开
    SYSTEM AND METHOD OF CALIBRATING POWER-ON GATING WINDOW FOR A TIME-TO-DIGITAL CONVERTER (TDC) OF A DIGITAL PHASE LOCKED LOOP (DPLL) 审中-公开
    用于校准QUICK ON时钟窗口系统和方法的时间数字转换器（TDC）的数字锁相环（DPLL）

    公开(公告)号：EP2274831A1

    公开(公告)日：2011-01-19

    申请号：EP09734274.5

    申请日：2009-04-22

    Applicant: QUALCOMM Incorporated

    Inventor： SUN, Bo ,  YANG, Zixiang ,  SAHOTA, Gurkanwal, Singh

    IPC: H03L7/085

    CPC classification number: H03L7/085 ,  H03L7/18 ,  H03L2207/50

    Abstract: A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.

    DIGITAL PHASE-LOCKED LOOP WITH GATED TIME-TO-DIGITAL CONVERTER
    49.
    发明公开
    DIGITAL PHASE-LOCKED LOOP WITH GATED TIME-TO-DIGITAL CONVERTER 有权
    与数字转换器TORGESTEUERTEM TIME数字锁相环路

    公开(公告)号：EP2232708A1

    公开(公告)日：2010-09-29

    申请号：EP08869551.5

    申请日：2008-12-24

    Applicant: QUALCOMM Incorporated

    Inventor： SUN, Bo ,  SAHOTA, Gurkanwal Singh ,  YANG, Zixiang

    IPC: H03L7/08 ,  H03L7/087

    CPC classification number: H03L7/0802 ,  H03L7/087

    Abstract: A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.

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