公开(公告)号：WO2019018056A1

公开(公告)日：2019-01-24

申请号：PCT/US2018/034467

申请日：2018-05-24

Applicant: QUALCOMM INCORPORATED

Inventor： LU, Ye ,  YUE, Yun ,  KONKAPAKA, Phanikumar ,  YANG, Bin ,  CHEN, Chuan-Hsing

IPC: H01L29/06 ,  H01L29/78

Abstract: A metal-oxide-semiconductor (MOS) device for radio frequency (RF) applications may include a guard ring. The guard ring may surround the MOS device and at least one other MOS device. The MOS device may further include a level zero contact layer coupled to a first interconnect layer through level zero interconnects and vias. The first interconnect layer may be for routing to the MOS device.

公开(公告)号：WO2018164759A1

公开(公告)日：2018-09-13

申请号：PCT/US2017/068971

申请日：2017-12-29

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Xia ,  YANG, Bin ,  TAO, Gengming

IPC: H01L21/322 ,  H01L21/265

Abstract: An integrated circuit (IC) device may include a substrate having an active device layer. The integrated circuit may also include a first defect layer. The first defect layer may have a first surface facing a backside of the active device layer. The integrated circuit may further include a second defect layer. The second defect layer may face a second surface opposite the first surface of the first defect layer.

公开(公告)号：WO2018140126A1

公开(公告)日：2018-08-02

申请号：PCT/US2017/062637

申请日：2017-11-20

Applicant: QUALCOMM INCORPORATED

Inventor： YANG, Bin ,  TAO, Gengming ,  LI, Xia

IPC: H01L29/737 ,  H01L23/367 ,  H01L29/417 ,  H01L29/08

Abstract: A heterojunction bipolar transistor may include an emitter (510), a base (502) contacting the emitter, a collector (514) contacting the base, a sub-collector (516) contacting the collector, and an electrical isolation layer (540) contacting the sub-collector. The heterojunction bipolar transistor also includes a backside heatsink (550) thermally coupled to the sub-collector and the collector. The backside heatsink may be aligned with a central axis of the emitter and the base.

公开(公告)号：WO2016118376A2

公开(公告)日：2016-07-28

申请号：PCT/US2016/013180

申请日：2016-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： YUAN, Jun ,  LI, Xia ,  YANG, Bin

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/7827 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/161 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391

Abstract: In a particular embodiment, an apparatus includes an electron tunnel structure. The electron tunnel structure includes a tunneling layer, a channel layer, a source layer, and a drain layer. The tunneling layer and the channel layer are positioned between the source layer and the drain layer. The transistor device further includes a high-k dielectric layer adjacent to the electron tunnel structure.

Abstract translation: 在特定实施例中，一种装置包括电子隧道结构。 电子隧道结构包括隧穿层，沟道层，源极层和漏极层。 隧穿层和沟道层位于源极层和漏极层之间。 晶体管器件还包括与电子隧道结构相邻的高k电介质层。

公开(公告)号：WO2015080873A1

公开(公告)日：2015-06-04

申请号：PCT/US2014/065539

申请日：2014-11-13

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Xia ,  KIM, Daeik Daniel ,  YANG, Bin ,  KIM, Jonghae ,  PERRY, Daniel Wayne

IPC: H01L27/07

CPC classification number: H01L29/7393 ,  G05F3/16 ,  H01L27/0705

Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.

Abstract translation: 一种方法包括根据场效应晶体管（FET）型操作，偏置第一栅极电压以使单相电流从晶体管的第一区域流过晶体管的第二区域。 该方法还包括偏置主体端子以使得双极电流能够根据双极结型晶体管（BJT）型操作从第一区域流动到第二区域。 单极电流与双极电流同时流动，在互补金属氧化物半导体（CMOS）技术中提供双模数字和模拟器件。

公开(公告)号：WO2015017030A1

公开(公告)日：2015-02-05

申请号：PCT/US2014/042142

申请日：2014-06-12

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Xia ,  YANG, Bin ,  KANG, Seung Hyuk

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L27/115 ,  H01L27/12

CPC classification number: H01L29/7883 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881

Abstract: A method for fabricating a multiple time programmable (MTP) device includes forming fins of a first conducting type on a substrate of a second conducting type. The method further includes forming a floating gate dielectric to partially surround the fins. The method also includes forming a floating gate on the floating gate dielectric. The method also includes forming a coupling film on the floating gate and forming a coupling gate on the coupling film.

Abstract translation: 一种制造多时间可编程（MTP）器件的方法包括在第二导电类型的衬底上形成第一导电类型的鳍片。 该方法还包括形成浮动栅极电介质以部分地围绕鳍片。 该方法还包括在浮栅电介质上形成浮栅。 该方法还包括在浮栅上形成耦合膜并在耦合膜上形成耦合栅极。

公开(公告)号：WO2013169776A3

公开(公告)日：2013-11-14

申请号：PCT/US2013/039947

申请日：2013-05-07

Applicant: QUALCOMM INCORPORATED

Inventor： YANG, Bin ,  LI, Xia ,  YUAN, Jun

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/47 ,  H01L29/66 ,  H01L29/10

Abstract: A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular embodiment, a CMOS device includes a silicon substrate, a dielectric insulator material on the silicon substrate, and an extension layer on the dielectric insulator material. The CMOS device further includes a gate in contact with a channel and in contact with an extension region. The CMOS device also includes a source in contact with the extension region and a drain in contact with the extension region. The extension region includes a first region in contact with the source and the gate and includes a second region in contact with the drain and the gate.

公开(公告)号：WO2023022881A1

公开(公告)日：2023-02-23

申请号：PCT/US2022/039303

申请日：2022-08-03

Applicant: QUALCOMM INCORPORATED

Inventor： YALLAMARAJU, Udayakiran Kumar ,  LI, Xia ,  DESHMUKH, Pankaj ,  GHANTASALA, Vajram ,  YANG, Bin ,  MISHRA, Vishal ,  JAGIRDAR, Bharatheesha Sudarshan ,  IYER, Arun Sundaresan ,  PHADKE, Amod ,  BHAT, Vanamali

IPC: H03K3/011 ,  H03K5/131 ,  H03K5/134 ,  H03K5/14 ,  H03K5/156 ,  H03K19/003

Abstract: A system (305) includes a first park circuit (310) having a signal input (312), an output (314), and a control input (316). The system also includes a first signal path (320) having an input (322) and an output (324), wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit (330) having a signal input (332), an output (334), and a control input (336), wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path (340) having an input (342) and an output (344), wherein the input of the second signal path is coupled to the output of the second park circuit.

公开(公告)号：WO2022177683A1

公开(公告)日：2022-08-25

申请号：PCT/US2022/012756

申请日：2022-01-18

Applicant: QUALCOMM INCORPORATED

Inventor： YANG, Bin ,  LI, Xia ,  YANG, Haining

IPC: H01L29/165 ,  H01L21/336 ,  H01L29/78

Abstract: An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge) (SiGe) buffer layer with a SiGe source (211S) and drain (211D) having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET (200) on a SiGe buffer layer (214) rather than directly on a Si substrate (216) and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.

公开(公告)号：WO2021252115A1

公开(公告)日：2021-12-16

申请号：PCT/US2021/031351

申请日：2021-05-07

Applicant: QUALCOMM INCORPORATED

Inventor： YANG, Haining ,  YANG, Bin ,  LI, Xia

IPC: B82Y10/00 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/775 ,  H01L27/092 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1079 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: A gate-all-around (GAA) transistor (304, 306) has an insulator (314) on a substrate (302). The GAA transistor also may have different crystalline structures for P-type work material and N-type work material. The GAA transistor includes one or more channels (308-1, 308-2, 308-3, 310-1, 310-2, 310-3) positioned between a source region (324, 328) and a drain (326, 330) region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material (312). At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate section (322) and a substrate, an insulator (314) is added on the substrate, which may be covered by layers (318, 320) from the gate stack. Further improvements may be made in performance of a circuit having both P-type work material and N-type work material by providing different crystalline lattice structures for the work material.