41.
    发明专利
    未知

    公开(公告)号:DE69432407D1

    公开(公告)日:2003-05-08

    申请号:DE69432407

    申请日:1994-05-19

    Abstract: A Power Integrated Circuit ("PIC") structure comprises a lightly doped semiconductor layer (2;2',2'') of the first conductivity type superimposed over a heavily doped semiconductor substrate (3) of a second conductivity type, wherein a Vertical IGBT and a driving and control circuitry comprising at least first conductivity type-channel MOSFETs are integrated; the MOSFETs are obtained inside well regions (15) of the second conductivity type which are included in at least one lightly doped region of the first conductivity type completely surrounded and isolated from the lightly doped layer (2;2',2'') of the first conductivity type by means of a respective isolated region (12,13) of a second conductivity type.

    42.
    发明专利
    未知

    公开(公告)号:DE69325994T2

    公开(公告)日:1999-12-23

    申请号:DE69325994

    申请日:1993-05-19

    Abstract: An integrated structure current sensing resistor for a power MOS device consists of a doped region (20,21,50) extending from a deep body region (2) of at least one cell (1a) of a first plurality of cells, constituting a main power device, to a deep body region (2) of a corresponding cell (1b) of a second smaller plurality of cells constituting a current sensing device.

    43.
    发明专利
    未知

    公开(公告)号:DE69325645T2

    公开(公告)日:1999-12-09

    申请号:DE69325645

    申请日:1993-04-21

    Abstract: An integrated structure protection device suitable for protecting a power MOS device from electro static discharges comprises a junction diode (9) comprising a first electrode made of a highly doped region (12) of a first conductivity type surrounded by a body region (11) of a second conductivity type and representing a second electrode of the junction diode (9), which in turn is surrounded by a highly doped deep body region (10) of said second conductivity type. The highly doped region (12) is connected to a polysilicon gate layer (7) representing the gate of the power MOS device, while the deep body region (10) is connected to a source region (6) of the power MOS.

    44.
    发明专利
    未知

    公开(公告)号:DE69131390T2

    公开(公告)日:1999-11-18

    申请号:DE69131390

    申请日:1991-04-11

    Abstract: The invention relates to a process for forming a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more power transistors with vertical current flow integrated in the same chip. The process allows optimization of the current-carrying capacity and the series drain resistance of the power stage and operating voltage in comparison with known structures by provision of one or more regions of high dopant concentration defined after growth of a first epitaxial layer.

    50.
    发明专利
    未知

    公开(公告)号:DE69331052T2

    公开(公告)日:2002-06-06

    申请号:DE69331052

    申请日:1993-07-01

    Abstract: An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region (3,7) of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first lightly doped ring (4) of the first conductivity type obtained in a first lightly doped epitaxial layer (2) of a second conductivity type and surrounding said diffused region (3,7), and a second lightly doped ring (8) of the first conductivity type, superimposed on and merged with said first ring (4), obtained in a second lightly doped epitaxial layer (6) of the second conductivity type grown over the first epitaxial layer (2).

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