公开(公告)号：JPH0653510A

公开(公告)日：1994-02-25

申请号：JP15092991

申请日：1991-05-28

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE ,  GRIMALDI ANTONIO

IPC: H01L21/8249 ,  H01L21/76 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/784

Abstract: PURPOSE: To maximize the breakdown voltage, without compromising the series resistance of a power stage and reliability of the device by making the min. distance of a structure junction from an embedded drain region shorter than or equal to that of this region from the junction of the peripheral region. CONSTITUTION: In a possible embodiment for the terminal of a power stage, a min. distance d1 between an embedded drain region 6 and this insulation region 9 is made smaller than that d2 between the buried drain region 9 from a junction 10, lying between a substrate and drain. In creating a device region 15, a substrate-drain junction 10 of an MOS power transistor must be connected to the region 9, as described above. The terminal length given from the region 9 is equal to the sum of the side face diffusions of the insulation regions, its photo-masked opening and error layout allowance. Its structure can maximize the operating voltage, without changing the series resistance of the power stage.

公开(公告)号：JPH07312372A

公开(公告)日：1995-11-28

申请号：JP14441494

申请日：1994-06-27

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE ,  LEONARDI SALVATORE ,  CACCIOLA GIOVANNA

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78

Abstract: PURPOSE: To provide integrated edge structure for a high voltage semiconductor device which does not need dopant of high diffusion coefficient and high temperature diffusion treatment. CONSTITUTION: Integrated edge structure for a high voltage semiconductor device provided with a PN junction formed by first conductivity type diffusion regions 3, 7 stretching from the upper surface of a semiconductor device is provided with the following; a first low doped ring 4 of a first conductivity type which is formed in a first low doped epitaxial layer 2 of a second conductivity type and surrounds the diffusion regions 3, 7, and a second low doped ring 8 of a first conductivity type which is formed in a second low doped epitaxial layer 5 of a second conductivity type formed on the first epitaxial layer 2, superposed on the first ring 4, and fusion-bonded to the ring.

公开(公告)号：JPH07321214A

公开(公告)日：1995-12-08

申请号：JP12146895

申请日：1995-05-19

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L27/088 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/78 ,  H01L21/06

Abstract: PURPOSE: To integrate power integrated circuit structures each having a driving and controlling circuit with an N and a P channel MOSFETs. CONSTITUTION: A power integrated circuit(PIC) structure has an N-type small doped semiconductor layer 2 and a large doped layer substrate 3 lower than the semiconductor layer 2. Power stages and driving and controlling circuits are integrated in the structure 3. Each power stage has a P-type large doped main body region 4 and a small doped main body region 5, and the driving and controlling circuit is provided with a P-type buried region 12 and a P-type large doped annular region 13 extending from a top face of the small doped N-type layer 2 to the buried region 12 and defining an N-type small doped region in a lateral direction. The driving and controlling circuit is completely surrounded by the P-type separation regions 12, 13. Moreover, the driving and controlling circuit has an N channel and a P channel MOSFETs formed respectively in an N-type and a P-type well regions 14, 15 included in the small doped region separated from the small doped layer 2. The annular region 13 and main body region 4 have the same depth to the top face of the small doped layer.

公开(公告)号：JPH06132538A

公开(公告)日：1994-05-13

申请号：JP32551992

申请日：1992-12-04

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： PAPARO MARIO ,  ZAMBRANO RAFFAELE

IPC: H01L29/78 ,  H01L21/76 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L29/784

Abstract: PURPOSE: To allow a dynamic insulating circuit-equipped control circuit of a semiconductor electronic device to reliably keep the semiconductor electronic device insulated even in a negatively charged transient state. CONSTITUTION: A switch S1 connects an insulating region to a ground. A switch S2 connects the insulating region to a collector or drain of a power transistor. A switch S3 connects the insulating region to a control circuit transistor region. A dynamic insulating circuit of a control circuit is constructed of a driving circuit CPI. Such dynamic insulating circuit closes the switch S1 when the potential of the ground or insulating region is lower than the voltage of the collector or drain of the power transistor or the potential of the control circuit region, closes the switch S2 and opens the switch S1 simultaneously when the voltage of the collector or drain of the power transistor is lower than the potential of the ground or insulating region, and closes the switch S3 and opens the switch S1 simultaneously when the potential of the control circuit region is lower than the potential of the ground or insulating region.

公开(公告)号：JPH08279554A

公开(公告)日：1996-10-22

申请号：JP7690896

申请日：1996-03-29

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/082 ,  H01L27/088 ,  H01L29/732 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a structure which isolates two regions of an integrated circuit. SOLUTION: In a method for forming a dialectic isolation structure between two regions of an integrated circuit where active regions of electronic components are already defined on a semiconductor substrate, the method includes a step for defining an isolation region 45 on a silicon oxide layer 42 which covers a silicon layer 41, a step for forming the isolation layer 45 by selectively etching the silicon layer 41, a step for growing a thermal oxide 43 on the inner surface of the isolation layer 45, a step for stacking a dialectic layer such that it aligns, and a step for oxidizing the stacked dialectic layer.

公开(公告)号：JPH08274109A

公开(公告)日：1996-10-18

申请号：JP27773995

申请日：1995-10-25

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE ,  FALLICO GIUSEPPE

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/423 ,  H01L29/732

Abstract: PROBLEM TO BE SOLVED: To improve the speed performance of a high-frequency bipolar- transistor structure. SOLUTION: The structure of a high-frequency bipolar transistor has an intrinsic base region 6 surrounded by an extrinsic base region 5 and has a first conductivity type base region 4 formed in a second conductivity type silicon layer 3 and a second conductivity type emitter region 7 formed at the inner side of the intrinsic base region 6. A first polysilicon layer 9 and a second polysilicon layer 15 are brought into contact with the extrinsic base region 5 and the emitter region 7, respectively. The first and second polysilicon layers 9 and 15 are brought into contact with a base metal electrode 13 and an emitter metal electrode 16, respectively. A silicide layer 8 is provided between the extrinsic base region 5 and the first polysilicon layer 9, and the extrinsic base resistance of the bipolar transistor is decreased.

公开(公告)号：JPH0645596A

公开(公告)日：1994-02-18

申请号：JP7441493

申请日：1993-03-31

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L29/78 ,  H01L21/331 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L29/784

Abstract: PURPOSE: To provide an integrated current-limiting device for a power MOS transistor, and a process for manufacturing the device. CONSTITUTION: A bipolar control transistor, constituting a part of an integrated current-limiting device, contains the following: second-type base regions 3, 4, 5, 7 which are approachable from a base contact, inside an epitaxial layer 2 on a first-type substrate 1, and regions of a first-type collector 5 and a first- type emitter 8 which are contained in the base regions. The base regions 3, 4, 5, 7 consist of at least a deep main region 3 which contains the region 8 and is doped with high concentration, a main region 5 which contains a region 6 and is doped with low concentration, the region 7 which contains completely the emitter region 8 and is doped with middle concentration, and a surface region 9 of the base regions 3-7, which are contained in the region between the regions 6 and 8.

公开(公告)号：DE69533773D1

公开(公告)日：2004-12-23

申请号：DE69533773

申请日：1995-03-31

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/082 ,  H01L27/088 ,  H01L29/732 ,  H01L29/78

Abstract: A novel process for forming, on a semiconductor substrate, a dielectric isolation structure between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been defined, comprises the steps of: defining an isolation region (45) on a layer of silicon oxide (42) overlying a silicon layer (41); selectively etching the silicon (41) to provide the isolation region (45); growing thermal oxide (43) over the interior surfaces of the isolation structure (45); depositing dielectric (46) conformingly; and oxidizing the deposited dielectric (46).

公开(公告)号：DE69433965D1

公开(公告)日：2004-09-30

申请号：DE69433965

申请日：1994-10-26

Applicant: CONS RIC MICROELETTRONICA

Inventor： FALLICO GIUSEPPE ,  ZAMBRANO RAFFAELE

IPC: H01L29/735 ,  H01L21/331

Abstract: A high-frequency lateral PNP transistor presenting a base region (63') laterally delimited by P type emitter (68) and collector (69) regions, and at the top by a surface portion (67) of the N type semiconductor body (63) housing the active area of the transistor. The surface portion (67) delimiting the base region (63') presents no formations of insulating material grown across the surface, so that the width (WB) of the base region (63') is reduced and ensures optimum dynamic characteristics of the transistor. The base contact (80, 82) may be located directly over the surface portion facing the base region (63'), to reduce the extrinsic base resistance and overall size of the device, or it may be located remotely and connected to the base region by a buried layer (62) and sinker region (88) to further reduce the base width.

公开(公告)号：DE69330556T2

公开(公告)日：2002-05-16

申请号：DE69330556

申请日：1993-05-13

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L21/822 ,  H01L27/04 ,  H01L27/02

Abstract: An integrated structure protection circuit suitable for protecting a power device (M) against overvoltages comprises a plurality of serially connected junction diodes (D1-D5), each having a first electrode, represented by a highly doped region (1) of a first conductivity type, and a second electrode represented by a medium doped or low doped region (2) of a second conductivity type. A first diode (D1) of said plurality has its first electrode (1) connected to a gate layer (5) of said power device (M) and its second electrode (2) connected to the second electrode (2) of at least one second diode (D2-D5) of said plurality, and said at least one second diode has its first electrode (1) connected to a drain region of the power device (M). The doping level of the second electrode (2) of the diodes (D1-D5) of said plurality is suitable to achieve sufficiently high breakdown voltage values.