公开(公告)号：JPH07312372A

公开(公告)日：1995-11-28

申请号：JP14441494

申请日：1994-06-27

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE ,  LEONARDI SALVATORE ,  CACCIOLA GIOVANNA

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78

Abstract: PURPOSE: To provide integrated edge structure for a high voltage semiconductor device which does not need dopant of high diffusion coefficient and high temperature diffusion treatment. CONSTITUTION: Integrated edge structure for a high voltage semiconductor device provided with a PN junction formed by first conductivity type diffusion regions 3, 7 stretching from the upper surface of a semiconductor device is provided with the following; a first low doped ring 4 of a first conductivity type which is formed in a first low doped epitaxial layer 2 of a second conductivity type and surrounds the diffusion regions 3, 7, and a second low doped ring 8 of a first conductivity type which is formed in a second low doped epitaxial layer 5 of a second conductivity type formed on the first epitaxial layer 2, superposed on the first ring 4, and fusion-bonded to the ring.

公开(公告)号：DE69331052D1

公开(公告)日：2001-12-06

申请号：DE69331052

申请日：1993-07-01

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE ,  LEONARDI SALVATORE ,  CACCIOLA GIOVANNA

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L21/329 ,  H01L21/336 ,  H01L21/761

Abstract: An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region (3,7) of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first lightly doped ring (4) of the first conductivity type obtained in a first lightly doped epitaxial layer (2) of a second conductivity type and surrounding said diffused region (3,7), and a second lightly doped ring (8) of the first conductivity type, superimposed on and merged with said first ring (4), obtained in a second lightly doped epitaxial layer (6) of the second conductivity type grown over the first epitaxial layer (2).

公开(公告)号：DE69420565T2

公开(公告)日：2000-03-30

申请号：DE69420565

申请日：1994-10-27

Applicant: CONS RIC MICROELETTRONICA

Inventor： CACCIOLA GIOVANNA ,  LEONARDI SALVATORE ,  MONTALBANO GIANPIERO

IPC: H01L21/8234 ,  H01L27/06 ,  H01L27/092

Abstract: The invention relates to a control circuit for semiconductor devices which is formed on a substrate (1) doped by a first dopant type, the integrated circuit comprising a first epitaxial layer (2) grown on the substrate (1) and doped by the first dopant type, and an isolation well (3) doped by a second dopant type, the control circuit comprising at least a first control transistor (M1) formed in a first well (8) doped by the second dopant type and formed in the insulation well (3). Thus, the control circuit comprises at least one N-channel MOS transistor accommodated within a well in direct contact with the isolation well to eliminate a buried layer that, in prior art arrangements, involved the presence of an undesired parasitic component.

公开(公告)号：DE69331052T2

公开(公告)日：2002-06-06

申请号：DE69331052

申请日：1993-07-01

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE ,  LEONARDI SALVATORE ,  CACCIOLA GIOVANNA

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L21/329 ,  H01L21/336 ,  H01L21/761

Abstract: An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region (3,7) of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first lightly doped ring (4) of the first conductivity type obtained in a first lightly doped epitaxial layer (2) of a second conductivity type and surrounding said diffused region (3,7), and a second lightly doped ring (8) of the first conductivity type, superimposed on and merged with said first ring (4), obtained in a second lightly doped epitaxial layer (6) of the second conductivity type grown over the first epitaxial layer (2).

公开(公告)号：DE69420565D1

公开(公告)日：1999-10-14

申请号：DE69420565

申请日：1994-10-27

Applicant: CONS RIC MICROELETTRONICA

Inventor： CACCIOLA GIOVANNA ,  LEONARDI SALVATORE ,  MONTALBANO GIANPIERO

IPC: H01L21/8234 ,  H01L27/06 ,  H01L27/092

Abstract: The invention relates to a control circuit for semiconductor devices which is formed on a substrate (1) doped by a first dopant type, the integrated circuit comprising a first epitaxial layer (2) grown on the substrate (1) and doped by the first dopant type, and an isolation well (3) doped by a second dopant type, the control circuit comprising at least a first control transistor (M1) formed in a first well (8) doped by the second dopant type and formed in the insulation well (3). Thus, the control circuit comprises at least one N-channel MOS transistor accommodated within a well in direct contact with the isolation well to eliminate a buried layer that, in prior art arrangements, involved the presence of an undesired parasitic component.