-
公开(公告)号：SG46128A1
公开(公告)日：1998-02-20
申请号：SG1995000286
申请日：1995-04-19
Applicant: SONY CORP
Inventor： MAEKAWA TOSHIKAZU
Abstract: The active matrix display device has a plurality of gate lines X provided on horizontal lines, a plurality of data lines Y provided on vertical lines, and a plurality of picture elements PXL provided at each intersection of both lines. The picture elements PXL provided horizontally and vertically constitute the display region 1. The vertical scanning circuit 2 scans vertically each gate line X sequentially, and selects picture elements on a respective one horizontal line every one horizontal period. The horizontal scanning circuit 3 scans each data line Y sequentially in one horizontal period, samples image signal Vsig, and writes by dot sequential scanning the image signal Vsig on picture elements PXL of a respective selected horizontal line. The data lines are defined in two sections, real data lines Y1, Y2, ...,YL provided in the display region 1, and dummy data lines YD1, YD2, YD3, and YD4 provided outside the display region, which dummy data lines intersect with the end section of the gate lines. The horizontal scanning circuit 3 scans horizontally the real data lines Y1, Y2,...,YL with a sampling timing overlapping a plurality of the real data lines, subsequently continues to scan the dummy data lines YD1, YD2, YD3 and YD4 with the overlapped sampling timing. Thereby, a band defect usually appearing on the side end of the screen when an active matrix display device is driven dot sequentially, is eliminated.
-
公开(公告)号：SG30353A1
公开(公告)日：1996-06-01
申请号：SG1995000283
申请日：1995-04-19
Applicant: SONY CORP
Inventor： MAEKAWA TOSHIKAZU , UCHINO KATSUHIDE
IPC: G09G3/36
-
公开(公告)号：GB2130036B
公开(公告)日：1986-06-11
申请号：GB8323730
申请日：1983-09-05
Applicant: SONY CORP
Inventor： SONEDA MITSUO , MAEKAWA TOSHIKAZU , OTSU KOUJI
Abstract: A signal translating circuit is disclosed in which an input signal is supplied to a source follower transistor, a bootstrap capacitive component is presented between the gate and source of the source follower transistor, the signal from the source follower transistor is supplied through a first transmission gate to a next stage, and also led out to an output terminal. Further, the circuit formed of the source follower transistor and the first transmission gate is sequentially connected and the source follower transistor and the first transmission gate are alternately driven with different phases to each other whereby the input signal is sequentially transmitted at each stage. Furthermore, a second transmission gate is connected between the output terminal of the source follower transistor and the ground in which after the output signal at the output terminal rises up and falls down once, the second transmission gate is turned on by the signal relating to the output from the stages following the succeeding stage to thereby make the level of the signal when the output signal at the output terminal falls down stable. Thus, undesired potential fluctuation is not generated on the output line.
-
公开(公告)号：DE69626713T2
公开(公告)日：2004-02-05
申请号：DE69626713
申请日：1996-04-10
Applicant: SONY CORP
Inventor： UCHINO KATSUHIDE , MAEKAWA TOSHIKAZU
Abstract: An active matrix display device comprising row gate lines, column signal lines and matrix pixels disposed at intersections of the gate and signal lines. The display device also includes a V shift register for line-sequentially scanning the gate lines and selecting pixels of one row during each horizontal scanning period, and a horizontal scanning circuit for sequentially sampling an actual video signal to the signal lines within one horizontal scanning period and writing the sampled actual video signal dot-sequentially in the pixels of one row. A precharge means is included as a characteristic requisite, wherein a first precharge signal is supplied simultaneously to the entire signal lines during a blanking period which precedes the horizontal scanning period, and further a second precharge signal is supplied sequentially to the signal lines prior to the step of sequentially sampling the actual video signal to the signal lines during each horizontal scanning period. This device is capable of preventing potential fluctuation that may otherwise be caused on a signal line by dot-sequential driving.
-
公开(公告)号：MY115352A
公开(公告)日：2003-05-31
申请号：MYPI9501024
申请日：1995-04-20
Applicant: SONY CORP
Inventor： MAEKAWA TOSHIKAZU
Abstract: THE ACTIVE MATRIX DISPLAY DEVICE HAS A PLURALITY OF GATE LINES Y PROVIDED ON HORIZONTAL LINES, A PLURALITY OF DATA LINES X PROVIDED ON VERTICAL LINES, AND A PLURALITY OF PICTURE ELEMENTS PROVIDED AT EACH INTERSECTION OF BOTH LINES. THE PICTURE ELEMENTS PXL PROVIDED HORIZONTALLY CONSTITUTE THE DISPLAY REGION 1. .THE VERTICAL SCANNING CIRCUIT 2 SCANS VERTICALLY EACH GATE LINE X SEQUENTIALLY, AND SELECTS PICTURE ELEMENTS ON ONE HORIZONTAL LINE EVERYONE HORIZONTAL PERIOD. THE HORIZONTAL SCANNING CIRCUIT 3 SCANS EACH DATA LINE Y SEQUENTIALLY IN ONE HORIZONTAL PERIOD, SAMPLES IMAGE SIGNAL VSIG, AND WRITES BY DOT SEQUENTIAL SCANNING THE IMAGE SIGNAL VSIG ON PICTURE ELEMENTS PXL ON SELECTED ONE HORIZONTAL LINE. THE DATA LINES ARE DEFINED TO TWO SECTIONS OF REAL DATA LINES YL, Y2, ...,YL PROVIDED IN THE DISPLAY REGION 1 AND DUMMY DATA LINES YD1, YD2, YD3, AND YD4 PROVIDED OUTSIDE THE DISPLAY REGION WHICH DUMMY; DATA LINES INTERSECT WITH THE END SECTION OF THE DATA LINES. THE HORIZONTAL SCANNING CIRCUIT 3 SCANS HORIZONTALLY ON THE REAL DATA LINES YL, Y2,...,YL WITH A SAMPLING TIMING OVERLAPPING A PLURALITY OF THE REAL DATA LINES, SUBSEQUENTLY CONTINUE TO SCAN ON THE DUMMY DATA TIMING. THEREBY BAND DEFECT ON THE SIDE END OF THE SCREEN WHEN AN ACTIVE MATRIX DISPLAY DEVICE IS DRIVEN DOT SEQUENTIALLY IS ELIMINATED.
-
Patent Agency Ranking
公开(公告)号：DE69804067T2
公开(公告)日：2002-11-14
申请号：DE69804067
申请日：1998-09-09
Applicant: SONY CORP
Inventor： MAEKAWA TOSHIKAZU
IPC: G02F1/133 , G09G3/20 , G09G3/36 , H01L29/786
Abstract: In an active matrix type LCD having a driving circuit unit which is capable of accepting digital signals having a signal level lower than the power source voltage of a horizontal driving circuit system combined with pixel unit, level shift circuits (15-1 to 15-n) for converting the level of sampled digital signals having a small amplitude to digital signals having a voltage of 0 to the power source voltage Vd are provided between sampling switches (12-1 to 12-n) and latch circuits (16-1 to 16-n). The structure is thus capable of accepting from the outside digital signals having a small signal amplitude and can be applied to a medium to large sized LCD.
-
公开(公告)号：NO20015907D0
公开(公告)日：2001-12-03
申请号：NO20015907
申请日：2001-12-03
Applicant: SONY CORP
Inventor： NAKAJIMA YOSHIHARU , MAEKAWA TOSHIKAZU
Abstract: This invention provides a liquid crystal display device having a partial screen display mode, in which a latch control circuit (17) first stores white data or black data as color data of one line to latch circuits (121), (131) at the beginning of an image non-display period and then repeatedly reads out and outputs the color data to respective column lines in a display area (11) until the display period ends, thereby stopping the operation to write data to the latch circuits (121), (131) substantially during the entire image non-display period.
-
公开(公告)号：DE69518872T2
公开(公告)日：2001-04-05
申请号：DE69518872
申请日：1995-04-21
Applicant: SONY CORP
Inventor： MAEKAWA TOSHIKAZU , UCHINO KATSUHIDE
Abstract: To restrict an oscillation in potential of a video line, caused by a high speed sampling rate, the active matrix display device is comprised of gate lines X in row, signal lines Y in column and liquid crystal pixels LC of matrix arranged at each of the crossing points of both lines. The V driver 1 scans in line sequence each of the gate lines X and selects the liquid crystal pixels LC in one row for every respective one horizontal period. The H driver 2 performs, in sequence, samplings of the video signal VSIG within one horizontal scanning period at each of the signal lines Y and performs a writing of the video signal VSIG by dot sequential scanning to the liquid crystal pixels LC in a respective selected row. The precharging means 4 supplies in sequence a predetermined precharging signal VPS prior to the sequential sampling of the video signal VSIG for each of the signal lines Y. This precharging means 4 is comprised of a plurality of switching elements PSW connected to an end part of each of the signal lines Y, and of a P driver 5 for supplying the precharge signal VPS to each of the signal lines Y through sequential controlling of ON or OFF of each of the switching elements PSW.
-
公开(公告)号：DE69517851T2
公开(公告)日：2001-01-11
申请号：DE69517851
申请日：1995-04-21
Applicant: SONY CORP
Inventor： MAEKAWA TOSHIKAZU , UCHINO KATSUHIDE
Abstract: To restrict an oscillation in the potential of a video line, caused by a high speed sampling rate, the active matrix display device is comprised of gate lines X forming rows, signal lines Y forming columns and liquid crystal pixels LC of the matrix arranged at crossing points of both lines. A V driver 1 scans in sequence each of the gate lines X and selects the liquid crystal pixels LC of one line for a corresponding horizontal period. The H driver 4 performs a sampling of the video signal VSIG for each of the signal lines Y and performs a writing of the video signal VSIG in the liquid crystal pixels LC the row selected during the corresponding horizontal period. Precharging means 5 supplies a predetermined precharging signal VPS to each of the signal lines Y just before writing the video signal VSIG for the liquid crystal pixels LC in one row. With such an arrangement as above, it is possible to reduce the charging or discharging amount in each of the signal lines Y when the video signal VSIG is sampled and further to restrict the oscillation of the potential in the video line 2.
-
公开(公告)号：DE69518872D1
公开(公告)日：2000-10-26
申请号：DE69518872
申请日：1995-04-21
Applicant: SONY CORP
Inventor： MAEKAWA TOSHIKAZU , UCHINO KATSUHIDE
Abstract: To restrict an oscillation in potential of a video line, caused by a high speed sampling rate, the active matrix display device is comprised of gate lines X in row, signal lines Y in column and liquid crystal pixels LC of matrix arranged at each of the crossing points of both lines. The V driver 1 scans in line sequence each of the gate lines X and selects the liquid crystal pixels LC in one row for every respective one horizontal period. The H driver 2 performs, in sequence, samplings of the video signal VSIG within one horizontal scanning period at each of the signal lines Y and performs a writing of the video signal VSIG by dot sequential scanning to the liquid crystal pixels LC in a respective selected row. The precharging means 4 supplies in sequence a predetermined precharging signal VPS prior to the sequential sampling of the video signal VSIG for each of the signal lines Y. This precharging means 4 is comprised of a plurality of switching elements PSW connected to an end part of each of the signal lines Y, and of a P driver 5 for supplying the precharge signal VPS to each of the signal lines Y through sequential controlling of ON or OFF of each of the switching elements PSW.
-
-
-
-
-
-
-
-
-
Search Results
60
records
(took 0.023 seconds)
