公开(公告)号：JP2586508B2

公开(公告)日：1997-03-05

申请号：JP21658987

申请日：1987-08-31

Applicant: SONY CORP

Inventor： NOGUCHI TAKASHI ,  HAYASHI HISAO ,  NEGISHI MICHIO ,  OOSHIMA TAKEFUMI ,  HAYASHI JUJI ,  MAEKAWA TOSHIICHI ,  MATSUSHITA TAKESHI

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/786

公开(公告)号：JPH098271A

公开(公告)日：1997-01-10

申请号：JP4614796

申请日：1996-03-04

Applicant: SONY CORP

Inventor： NOGUCHI TAKASHI ,  HAYASHI HISAO ,  MAEKAWA TOSHIICHI

IPC: H01L27/146 ,  H01L31/10 ,  H04N1/028 ,  H04N5/335 ,  H04N5/369 ,  H04N5/374

Abstract: PROBLEM TO BE SOLVED: To reduce the number of manufacturing processes of a light receiving device so as to improve the manufacturing efficiency of the device by forming one electrode of a semiconductor light receiving element and substrate area of a switching transistor in the same process. SOLUTION: A light receiving device in which the so-called Schottky PIN photodiode 34 constituting semiconductor light receiving elements is constituted can be manufactured by forming a base electrode 35 which is one of the electrodes of a semiconductor light receiving element by implanting arsenic ions As' into a single-crystal silicon layer as an N-type impurity and forming thereon a hydrogenated amorphous silicon layer 6 constituting a high-resistance intrinsic semiconductor layer and an indium oxide layer 7 constituting a transparent conductive film on the electrode 35, and then, connecting an aluminum electrode which is the other electrode of the light receiving element to the indium oxide layer 7 through the opening 8A of an SiO2 layer. Therefore, a single-crystal silicon layer 11 constituting the substrate area of an n-type MOSFET 3 for switching and another single-crystal silicon layer 44 constituting the substrate of the base electrode 35 of the diode 34 can be formed in the same process.

公开(公告)号：JP2550998B2

公开(公告)日：1996-11-06

申请号：JP13552287

申请日：1987-05-29

Applicant: SONY CORP

Inventor： NOGUCHI TAKASHI ,  MORITA YASUSHI

IPC: H01L21/20 ,  H01L21/263 ,  H01L21/84

公开(公告)号：JPH08107067A

公开(公告)日：1996-04-23

申请号：JP14502295

申请日：1995-06-12

Applicant: SONY CORP

Inventor： NOGUCHI TAKASHI ,  HAYASHI HISAO ,  OSHIMA TAKEFUMI

IPC: H01L21/20 ,  H01L21/265 ,  H01L21/324 ,  H01L21/336 ,  H01L29/786

Abstract: PURPOSE: To manufacture a semiconductor chip showing a high carrier mobility with high reproducibility. CONSTITUTION: Si ions are implanted into a polycrystalline silicon layer which is formed by an LP-CVD method so as to obtain the ESR center density not less than 1.03×10 /cm and, after the layer is sufficiently made to be amorphous, a furnace annealing(FA) is performed at 600 deg.C as a first step annealing and then a rapid thermal annealing(RTA) at 1000 deg.C as a second step annealing. With this constitution, the large grain size of the polycrystalline silicon layer can be realized and a high carrier mobility can be achieved.

公开(公告)号：JPH07124776A

公开(公告)日：1995-05-16

申请号：JP29739993

申请日：1993-11-02

Applicant: SONY CORP

Inventor： NOGUCHI TAKASHI ,  OGAWA TORU

IPC: B23K26/06 ,  B23K26/073 ,  B23K26/352 ,  H01L21/22 ,  H01L21/26 ,  H01L21/265 ,  H01L21/268 ,  H01L21/31 ,  H01L21/324 ,  B23K26/00

Abstract: PURPOSE:To enable a surface treatment by irradiating a wide area by one shot, to enable scanning of a laser beam, to make an oscillation output stable, and to improve the uniformity of the surface treatment by providing a laser beam oscillator with a high output. CONSTITUTION:A laser beam oscillator 11 generating a laser beam 21, for instance, with >=2J/pulse, an attenuator 12 in the optical path of the laser beam 21 generated from the laser beam oscillator 11, a laser beam scanning means 13 scanning the laser beam 21 in the X-y axis direction and a beam homogenizer 14 are successively provided on a surface treatment device 1. Further, a chamber 15 is installed, and a stage 16 on which an object 91 to be worked is loaded, is provided in the chamber 15. Also, a reticle is provided between the beam homogenizer 14 and the chamber 15, and an alignment means and the adjustment means of a laser beam generation output, are provided on the surface treatment device 1. Further, a shutter is installed in the optical path of the laser beam 21.

公开(公告)号：JPH07115188A

公开(公告)日：1995-05-02

申请号：JP28450493

申请日：1993-10-18

Applicant: SONY CORP

Inventor： MATSUMOTO KOICHI ,  NOGUCHI TAKASHI ,  KUBOTA MICHITAKA

IPC: H01L21/336 ,  H01L29/78

Abstract: PURPOSE:To suppress a capacitance between a gate electrode and a drain electrode to improve radio frequency characteristics and reduce the resistances of the low impurity concentration diffused layers of source/drain regions which have LDD structures and shallow junctions. CONSTITUTION:A gate insulating film 12 and a gate electrodes 13 are built up on a semiconductor substrate 11. Source/drain regions 19 and 20 having LDD structures composed of low impurity concentration diffused layers 15 and 16 and high impurity concentration diffused layers 17 and 18 are formed on the parts of the semiconductor substrate 11 on both the sides of the gate electrode 13. Further, first side wall spacers 21 are formed on both the sides of the gate electrode 13 and on the low impurity concentration diffused layers 15 and 16 and second side wall spacers 22 which have a lower specific inductive capacity than the first side wall spacers 21 are formed on both the side walls of the first side wall spacers 21 and on the parts of the high impurity concentration layers 17 and 18. Further, stacked diffused layers 23 and 24 on which silicide layers 25 and 26 are formed are formed on both the side walls of the second wall spacers 22 and on the high impurity concentration diffused layers 17 and 18.

公开(公告)号：JPH06302613A

公开(公告)日：1994-10-28

申请号：JP8448793

申请日：1993-04-12

Applicant: SONY CORP

Inventor： NOGUCHI TAKASHI ,  TSUKAMOTO HIRONORI

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/786 ,  H01L29/784

Abstract: PURPOSE:To improve controllability of the length of a short channel upon annealing by forming a pattern of a series of source/drain region formation portions of a plurality of thin film transistors and thereafter separating the mutually adjacent source/drain region formation portions of the adjacent thin film transistors. CONSTITUTION:A semiconductor thin film 2 formed on a substrate 1 includes a channel formation portion 11 of each thin film transistor and a source/drain region formation portion 12 having a wider portion. There is formed an island 21 yielded by patterning the adjacent source/drain region formation regions of each thin film transistor into a pattern where the source/drain region formation regions are integrally continuously disposed. Thereafter, an annealing processing is performed by the use of ultraviolet ray irradiation to form an intrinsic channel portion and a source/drain region 7 for simultaneous formation of a plurality of FETs. The adjacent source/drain region formation portions 12 between the adjacent thin film transistors are separated from each other to form a second island 22. Thus, heat storage is restricted.

公开(公告)号：JPH06177355A

公开(公告)日：1994-06-24

申请号：JP32684292

申请日：1992-12-07

Applicant: SONY CORP

Inventor： NOGUCHI TAKASHI

IPC: H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11

Abstract: PURPOSE:To compose a laminated static semiconductor memory having stable characteristics using an amorphous semiconductor. CONSTITUTION:A p-channel insulating field-effect transistor is formed on a semiconductor substrate 1 and then an n-channel insulating gate transistor is formed on an amorphous semiconductor thin film 10 also formed on the semiconductor substrate 1.

公开(公告)号：JPH06177148A

公开(公告)日：1994-06-24

申请号：JP32814592

申请日：1992-12-08

Applicant: SONY CORP

Inventor： NOGUCHI TAKASHI

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L29/784

Abstract: PURPOSE:To enhance gate-drain (source) breakdown voltage by oxidizing a gate electrode to form an oxide film, removing the oxide film, implanting impurity ions using the gate electrode as a mask, thereby forming a lightly doped drain region and a source region. CONSTITUTION:A polycrystalline semiconductor gate electrode 3 is formed with a predetermined width on a semiconductor substrate through a gate insulation layer 2 and the surface of the gate electrode 3 is then oxidized to form an oxide film of predetermined thickness. The oxide film 4 is then removed by etching to leave the gate electrode 3 of width L1 which is used as a mask in the implantation of impurity ions thus forming a lightly doped drain and source regions 5, 6 on the semiconductor substrate 1. This method allows formation of an LDDMOS transistor having channel length shorter than that attainable by photolithography for forming the gate electrode 3 while enhancing gate-drain (source) breakdown voltage.

公开(公告)号：JPH0637112A

公开(公告)日：1994-02-10

申请号：JP18665392

申请日：1992-07-14

Applicant: SONY CORP

Inventor： NOGUCHI TAKASHI

IPC: H01L21/20 ,  H01L21/268 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786 ,  H01L29/784

Abstract: PURPOSE:To improve the performance of a thin film transistor by sufficiently suppressing the generation of grain boundaries in the direction crossing the moving direction of carriers so that the film quality of an active layer can be surely made uniform and the fluctuation of mobility, etc., of the transistor can be suppressed even when the transistor has a relatively large channel width. CONSTITUTION:After forming at least an amorphous semiconductor layer on a substrate 1, crystal growing nuclie are formed linearly in the area where the active area of the layer 3 is formed by irradiating a linear pattern extended in the direction perpendicular to the moving direction of carriers with radiation ray and a single-crystal area 14 18 formed by growing a solid-phase crystal from the core by low-temperature heating.