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    41.
    发明专利
    未知

    公开(公告)号：FR2810783A1

    公开(公告)日：2001-12-28

    申请号：FR0008215

    申请日：2000-06-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: G11C17/16 ,  G11C17/18 ,  G11C29/00 ,  H03K3/353

    Abstract: A NAND gate (4) has an input connected to a common point between an auto-stable assembly (1) of latches and a blowable assembly (3). A second input is connected to a control input of an electronic circuit. A breaker (5) is controlled by the output of the logic gate and arranged between the auto-stable assembly and ground. An Independent claim is included for: (1) a process for reading a blowable element

    42.
    发明专利
    未知

    公开(公告)号：FR2809526A1

    公开(公告)日：2001-11-30

    申请号：FR0006645

    申请日：2000-05-24

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: G11C7/06 ,  G11C17/12 ,  G11C7/12

    Abstract: The invention concerns a ROM circuit (40) comprising columns of storage cells, each column being connected to a bit site (BLi, BLi+1), wherein the columns are arranged in groups of two adjacent columns, each column of a group capable of being selectively activated relative to the other column of the group, thereby enabling the elimination of a connection to the ground of columns and the design of efficient reading amplifiers.

    Memory cell with low power consumption, comprising MOS transistors and capacitors with leakage-current integrated resistances
    44.
    发明专利
    Memory cell with low power consumption, comprising MOS transistors and capacitors with leakage-current integrated resistances 未知

    公开(公告)号：FR2793939A1

    公开(公告)日：2000-11-24

    申请号：FR9906590

    申请日：1999-05-19

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD ,  BOREL JOSEPH

    IPC: G11C11/22 ,  G11C11/412 ,  H01L27/11 ,  G11C11/41 ,  G11C11/24 ,  G11C11/40

    Abstract: The memory cell comprises the first and second MOS transistors (M1,M2) with the sources (A1,B1) connected via capacitors (C1,C2) having leakage-current resistances to the supply voltage (PVdd), and the drains connected to the ground; the gate of the second transistor is connected to the source of the first transistor and to the drain of a third MOS transistor (M3); the gate of the first transistor is connected to the source of the second transistor and to the drain of a fourth MOS transistor (M4). The gates of third and fourth transistors are connected to the word line (WL) of the cell, and the sources are connected to the bit line and the complement bit line (BL,CBL). A variant of the memory cell comprises the first and second MOS transistors (M1,M2), and the third MOS transistor (M3) with the gate connected to the word line (WL) and the source connected to the bit line (BL); the resistances are constituted by the leakage-current effect of capacitors (C1,C2). The capacitors (C1,C2) contain a ferroelectric dielectric. In a monolithic implementation of memory cell in a semiconductor substrate, at least one of the capacitors utilizes a part of the source region of one of the two transistors (M1,M2) as the first electrode, where insulating and conducting layers constituting the dielectric and the second electrode are deposited and etched. In the case of the variant containing three MOS transistors, at least one of the capacitors (C1,C2) utilizes the gate electrode of one of the two transistors (M1,M2) as the first electrode, where the insulating and conducting layers are deposited and etched. The dielectric layers are treated for implantation by diffusion of a dopant to obtain a low density of holes in the dielectric. The cell also comprises means for a brief interruption of the supply voltage (PVdd) connected to the drains of two transistors (M1,M2) at the time of each switching of cell.

    Dynamic memory cell with addressing commutation, comprising a capacitor with first terminal connected to the bit line via a transistor, and second terminal connected to a supplementary row line
    46.
    发明专利
    Dynamic memory cell with addressing commutation, comprising a capacitor with first terminal connected to the bit line via a transistor, and second terminal connected to a supplementary row line 未知

    公开(公告)号：FR2784493A1

    公开(公告)日：2000-04-14

    申请号：FR9812843

    申请日：1998-10-09

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: G11C11/4074 ,  G11C11/40

    Abstract: The memory cell for an integrated circuit memory unit comprises a transistor (T) of MOS (metal-oxide-silicon) type for selection, and a capacitor (C) with the first terminal (SN) connected via the transistor to the bit line (2). The gate (G) of the transistor is connected to the word line (1), and the second terminal of the capacitor is connected to a supplementary row line (3), which potential varies according to the addressing of the corresponding word line. The source (S) of the transistor (T) is connected to the first terminal (SN) of the capacitor (C), and the drain (D) to the bit line (2). The voltage level in the memory cell is determined by the potential of the row line (3) during the period of addressing the cell. The word line (1) is addressable between two potentials which do not exceed the supply potentials of the memory circuit, e.g. Vdd and zero, that of the ground. The addressing procedure includes a change of the potential of the second terminal of the capacitor, and the stationary potential is intermediate between the two supply potentials, e.g. equal to Vdd/2. The addressing potential at the second terminal of the capacitor corresponds to a supply potential.

    48.
    发明专利
    未知

    公开(公告)号：DE60118321D1

    公开(公告)日：2006-05-18

    申请号：DE60118321

    申请日：2001-06-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: G11C17/14 ,  G06F11/20 ,  G11C17/16 ,  G11C17/18

    Abstract: A NAND gate (4) has an input connected to a common point between an auto-stable assembly (1) of latches and a blowable assembly (3). A second input is connected to a control input of an electronic circuit. A breaker (5) is controlled by the output of the logic gate and arranged between the auto-stable assembly and ground. An Independent claim is included for: (1) a process for reading a blowable element

    49.
    发明专利
    未知

    公开(公告)号：DE69923900T2

    公开(公告)日：2006-04-06

    申请号：DE69923900

    申请日：1999-09-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD

    IPC: G11C5/02 ,  G11C7/00 ,  G11C7/10 ,  G11C11/4096

    Abstract: The memory realized in an integrated circuit chip (2') comprises a matrix network of cells divided in sections (S), rows of amplifiers for column decoding (CDEC) with outputs interconnected to decoded bit lines, each comprising two perpendicular sections, one in the row direction for connecting directly each decoded bit line to the input/output (I/O) stage at the extremity of rows. The circuits for row decoding (RDEC), predecoding (PREDEC), input/output (I/O), and control (CONTROL) are located in the same section as the bus for address (ADD), data (DATA) and control (CTR) signals. The change of direction within two sections of the bit line is carried out without active element, by direct interconnection. The memory cell contains a transistor connected to a capacitor, and the amplifier for column decoding is directly connected to the local bit line interconnecting the drains of transistors in the same section. The circuits (PREDEC, RDEC, I/O) can be located on both sides of the integrated circuit chip. The number of rows of memory cells per section is selected to have the signal/noise ratio higher than 1/10 at inputs of amplifiers for column decoding.

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