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    Memory cell with low power consumption, comprising MOS transistors and capacitors with leakage-current integrated resistances
    2.
    发明专利
    Memory cell with low power consumption, comprising MOS transistors and capacitors with leakage-current integrated resistances 未知

    公开(公告)号：FR2793939A1

    公开(公告)日：2000-11-24

    申请号：FR9906590

    申请日：1999-05-19

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRANT RICHARD ,  BOREL JOSEPH

    IPC: G11C11/22 ,  G11C11/412 ,  H01L27/11 ,  G11C11/41 ,  G11C11/24 ,  G11C11/40

    Abstract: The memory cell comprises the first and second MOS transistors (M1,M2) with the sources (A1,B1) connected via capacitors (C1,C2) having leakage-current resistances to the supply voltage (PVdd), and the drains connected to the ground; the gate of the second transistor is connected to the source of the first transistor and to the drain of a third MOS transistor (M3); the gate of the first transistor is connected to the source of the second transistor and to the drain of a fourth MOS transistor (M4). The gates of third and fourth transistors are connected to the word line (WL) of the cell, and the sources are connected to the bit line and the complement bit line (BL,CBL). A variant of the memory cell comprises the first and second MOS transistors (M1,M2), and the third MOS transistor (M3) with the gate connected to the word line (WL) and the source connected to the bit line (BL); the resistances are constituted by the leakage-current effect of capacitors (C1,C2). The capacitors (C1,C2) contain a ferroelectric dielectric. In a monolithic implementation of memory cell in a semiconductor substrate, at least one of the capacitors utilizes a part of the source region of one of the two transistors (M1,M2) as the first electrode, where insulating and conducting layers constituting the dielectric and the second electrode are deposited and etched. In the case of the variant containing three MOS transistors, at least one of the capacitors (C1,C2) utilizes the gate electrode of one of the two transistors (M1,M2) as the first electrode, where the insulating and conducting layers are deposited and etched. The dielectric layers are treated for implantation by diffusion of a dopant to obtain a low density of holes in the dielectric. The cell also comprises means for a brief interruption of the supply voltage (PVdd) connected to the drains of two transistors (M1,M2) at the time of each switching of cell.

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