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公开(公告)号:FR2803925A1
公开(公告)日:2001-07-20
申请号:FR0000605
申请日:2000-01-18
Applicant: ST MICROELECTRONICS SA
Inventor: POMET ALAIN
Abstract: The delay ( delta 1, delta 2) between two sync pulses, calculated with respect to internal time unit (ut), is measured with respect to preceding pulse of clock signal (CK100). The two delays, a measure of the number of reference clock periods and of the number of clock pulses (N), are applied to start a computer (10) which calculates a corresponding period (T6) and to initialize stop counting (C2) activated at each regen. cycle so as to output a regenerated clock pulse (CKGEN). Clock signal regeneration from at least two synchronizing pulses (IS1,IS2) transmitted on an external USB bus, in an integrated circuit (C1) having an internal oscillator (2) designed to provide a reference clock signal (CK100). A unit (130) defines a unit of time (ut) and an associated measuring unit (131) provides a precise measure in the time unit of the delay between two synchronizing pulses each with respect to a preceding reference clock signal (CK100). The definition unit (130) includes a train of delay circuits (P0,P1,....) at the input of which is applied the reference clock signal (CK100). The delay applied by each circuit being equal to the time unit (ut). The measuring unit (131) includes a flip flop (B0) by the delay circuit (P0) and a read register (RL). The input of delay circuit being applied as input (D) of the associated flip flop, whose output )Q) is applied on a corresponding input of the read register.
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公开(公告)号:FR2802733A1
公开(公告)日:2001-06-22
申请号:FR9916180
申请日:1999-12-21
Applicant: ST MICROELECTRONICS SA
Inventor: POMET ALAIN
IPC: G06K19/073 , H03K3/037 , H03K3/3562
Abstract: A master-slave D type flip-flop circuit includes a power consumption masking circuit including a reference stage in parallel with a master and a slave stage of the flip-flop circuit. This structure advantageously provides a switching of the flip-flop circuit on each of the leading and trailing edges of the clock signal for the sequencing of the flip-flop circuit.
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公开(公告)号:FR2794258A1
公开(公告)日:2000-12-01
申请号:FR9906743
申请日:1999-05-26
Applicant: ST MICROELECTRONICS SA
Inventor: POMET ALAIN , PLESSIER BERNARD
Abstract: A selection device (22o-22a-1) and (23o-23a-1) provides either '0' and '0', or '0' and A, or A and '0', or A and A, on first and second according to even and odd bit of B. An accumulator (24-28) and (29o-29a-i) is connected to the first and second outputs to add the data from first and second outputs to an accumulated result. An Independent claim is included for: (a) a method of multiplying of two numbers
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