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公开(公告)号：JP2001237825A
公开(公告)日：2001-08-31
申请号：JP2000366035
申请日：2000-11-30
Applicant: ST MICROELECTRONICS SA
Inventor： POMET ALAIN , PLESSIER BERNARD , SOURGEN LAURENT
Abstract: PROBLEM TO BE SOLVED: To prevent a data element moving via a bus from being identified or to hardly make the data element identified. SOLUTION: In the electronic component provided with a 2-way bus DATA- BUS through which the data element is moved at a speed of a clock signal PHI between peripheral devices P1, P2, P3 and a central processing unit CPU, each of the central processing unit CPU and at least one peripheral device P1 is provided with a data encryption/decoding cell Kcell employing respectively the same private key KEY, a random signal Kin synchronously with the clock signal PHI is uniquely outputted at each clock cycle of each cell as the current value of the private key and applied to the respective cells through a unidirectional transmission line.
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公开(公告)号：DE60023770T2
公开(公告)日：2006-06-01
申请号：DE60023770
申请日：2000-02-18
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE-YVAN , ROMAIN FABRICE , PLESSIER BERNARD , HENNEBOIS BRIGITTE
Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.
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公开(公告)号：FR2789247A1
公开(公告)日：2000-08-04
申请号：FR9900930
申请日：1999-01-28
Applicant: ST MICROELECTRONICS SA
Inventor： PLESSIER BERNARD , DO TIEN DUNG
Abstract: System has synchronizing cells (7,8) clocked by a primary clock signal (H0) and outputting secondary clock signals (H1,H2) as requested by validation signals (V1,V2), which respectively activate first and second modules. The cells have means (10) for locking each signal (V1) associated with means (11,12) for equalizing the secondary clock signal (H1) time period and for coordinating signals (H1,H2).
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公开(公告)号：DE60030074T2
公开(公告)日：2007-03-29
申请号：DE60030074
申请日：2000-11-29
Applicant: ST MICROELECTRONICS SA
Inventor： POMET ALAIN , PLESSIER BERNARD , SOURGEN LAURENT
Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.
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公开(公告)号：DE60023770D1
公开(公告)日：2005-12-15
申请号：DE60023770
申请日：2000-02-18
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE-YVAN , ROMAIN FABRICE , PLESSIER BERNARD , HENNEBOIS BRIGITTE
Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.
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Patent Agency Ranking
公开(公告)号：FR2789247B1
公开(公告)日：2004-10-15
申请号：FR9900930
申请日：1999-01-28
Applicant: ST MICROELECTRONICS SA
Inventor： PLESSIER BERNARD , DO TIEN DUNG
Abstract: In the field of systems for the synchronization of modular electronic circuits, a system is provided for the coordinated activation of the modules. This system includes synchronization cells that have their pace set by a primary clock signal and deliver secondary clock signals controlled intermittently by the enabling signals to respectively activate the modules. The cells lock the state of each enabling signal associated with a regulator for regulating the periodicity of the change in state of each secondary clock signal and coordinating the changes in states of the secondary clock signals with one another. The system can be advantageously applied to electronic circuits having very high frequency data processing modules, especially those providing for the multiplexing of the transmissions of data carried out by each module.
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公开(公告)号：DE69802016T2
公开(公告)日：2002-01-31
申请号：DE69802016
申请日：1998-08-26
Applicant: ST MICROELECTRONICS SA
Inventor： PLESSIER BERNARD
Abstract: At least one shift register (17) receives at least one word of Bt bits of the dividend and performs Bt shifts of Bt-1 bits with input and output connected via multiplexer (16) to output the word in reverse order. At least one shift register (22) receives at least one word of Bt bits of the quotient and performs a similar series of shifts with a multiplexer (21) to output the word in reverse order. An Independent claim is also included for the modular arithmetic coprocessor.
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公开(公告)号：DE60030074D1
公开(公告)日：2006-09-28
申请号：DE60030074
申请日：2000-11-29
Applicant: ST MICROELECTRONICS SA
Inventor： POMET ALAIN , PLESSIER BERNARD , SOURGEN LAURENT
Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.
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公开(公告)号：DE69817928D1
公开(公告)日：2003-10-16
申请号：DE69817928
申请日：1998-07-03
Applicant: ST MICROELECTRONICS SA
Inventor： POMET ALAIN , PLESSIER BERNARD
Abstract: A sequential access memory consists of a number (N) of recording elements, each memorising one bit of information and distributed into P groups, each of L elements. In an initial operating phase, with a duration corresponding to P-1 consecutive clock signal periods, only the last element in each group, connected in series, is activated. During a second operating phase, with a duration corresponding to a single clock signal period, all the elements are activated.
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公开(公告)号：FR2794258B1
公开(公告)日：2001-09-14
申请号：FR9906743
申请日：1999-05-26
Applicant: ST MICROELECTRONICS SA
Inventor： POMET ALAIN , PLESSIER BERNARD
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