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    ELECTRONIC SAFETY COMPONENT
    1.
    发明专利
    ELECTRONIC SAFETY COMPONENT 失效

    公开(公告)号：JP2001237825A

    公开(公告)日：2001-08-31

    申请号：JP2000366035

    申请日：2000-11-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： POMET ALAIN ,  PLESSIER BERNARD ,  SOURGEN LAURENT

    IPC: H04L9/20 ,  H04L9/00 ,  H04L9/08 ,  H04L9/10

    Abstract: PROBLEM TO BE SOLVED: To prevent a data element moving via a bus from being identified or to hardly make the data element identified. SOLUTION: In the electronic component provided with a 2-way bus DATA- BUS through which the data element is moved at a speed of a clock signal PHI between peripheral devices P1, P2, P3 and a central processing unit CPU, each of the central processing unit CPU and at least one peripheral device P1 is provided with a data encryption/decoding cell Kcell employing respectively the same private key KEY, a random signal Kin synchronously with the clock signal PHI is uniquely outputted at each clock cycle of each cell as the current value of the private key and applied to the respective cells through a unidirectional transmission line.

    METHOD AND CIRCUIT FOR LOCAL CLOCK GENERATION AND SMARTCARD INCLUDING IT THEREON
    2.
    发明申请
    METHOD AND CIRCUIT FOR LOCAL CLOCK GENERATION AND SMARTCARD INCLUDING IT THEREON 审中-公开
    用于本地时钟产生的方法和电路以及包括它的智能卡

    公开(公告)号：WO2007042928A2

    公开(公告)日：2007-04-19

    申请号：PCT/IB2006002860

    申请日：2006-10-06

    Applicant: AXALTO SA ,  ST MICROELECTRONICS SA ,  LEYDIER ROBERT ,  POMET ALAIN ,  DUVAL BENJAMIN

    Inventor： LEYDIER ROBERT ,  POMET ALAIN ,  DUVAL BENJAMIN

    IPC: G06F1/04 ,  H03L7/197

    CPC classification number: G06F1/04 ,  H03K5/133 ,  H03K5/135 ,  H03K5/156 ,  H03K2005/00058 ,  H04L7/0338

    Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal f(0) to f(2 i -1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal f(0) to j(2 i -1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal f(0) to f(2 i -1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

    Abstract translation: 一个延迟电路插入时钟恢复电路内的开环，以提高时钟恢复的精度。 一个振荡器信号f（0）至f（2-i-1）被提供有基本的时间步长。 在接收到的比特流内测量与比特持续时间相对应的时间步长的合理数量。 振荡器信号f（0）至j（2≤I-1）被变换成具有与所述时钟信号的有效边沿同时具有至少一个振荡器信号f（0）至f （2 i），两个连续的有效边缘被分离成与时间步长数的整数部分成比例的时间长度。 计算时间延迟与时间步长数的小数部分成比例。 时钟信号CK的下一个有效沿延迟所述计算的延迟。

    Device for the regeneration of a clock signal
    3.
    发明授权
    Device for the regeneration of a clock signal 有权
    用于再生时钟信号的装置

    公开(公告)号：US6362671B2

    公开(公告)日：2002-03-26

    申请号：US77136401

    申请日：2001-01-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： MALHERBE ALEXANDRE ,  MARINET FABRICE ,  POMET ALAIN

    IPC: G06F13/42 ,  G06K19/07 ,  H03K5/01

    CPC classification number: G06K19/07 ,  G06F13/426

    Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

    Abstract translation: 用于从外部串行总线再生时钟信号的装置包括环形振荡器和计数器。 环形振荡器提供时钟信号的n个相位。 在这n个阶段中，使用一个相作为参考，并将其应用于计数器。 因此，可以对从总线接收的第一脉冲和第二脉冲之间的整个参考时钟信号周期的数量进行计数。 在接收到第二脉冲时读取振荡器中的相位状态，确定与基准时钟信号和总线的第二脉冲之间的相位延迟相对应的电流相位。 通过使用还包括环形振荡器和计数器的再生装置，可以高精度地重新生成总线的时钟信号。

    5.
    发明专利
    未知

    公开(公告)号：DE60118815D1

    公开(公告)日：2006-05-24

    申请号：DE60118815

    申请日：2001-01-17

    Applicant: ST MICROELECTRONICS SA

    Inventor： POMET ALAIN

    IPC: G06F13/42

    Abstract: The delay ( delta 1, delta 2) between two sync pulses, calculated with respect to internal time unit (ut), is measured with respect to preceding pulse of clock signal (CK100). The two delays, a measure of the number of reference clock periods and of the number of clock pulses (N), are applied to start a computer (10) which calculates a corresponding period (T6) and to initialize stop counting (C2) activated at each regen. cycle so as to output a regenerated clock pulse (CKGEN). Clock signal regeneration from at least two synchronizing pulses (IS1,IS2) transmitted on an external USB bus, in an integrated circuit (C1) having an internal oscillator (2) designed to provide a reference clock signal (CK100). A unit (130) defines a unit of time (ut) and an associated measuring unit (131) provides a precise measure in the time unit of the delay between two synchronizing pulses each with respect to a preceding reference clock signal (CK100). The definition unit (130) includes a train of delay circuits (P0,P1,....) at the input of which is applied the reference clock signal (CK100). The delay applied by each circuit being equal to the time unit (ut). The measuring unit (131) includes a flip flop (B0) by the delay circuit (P0) and a read register (RL). The input of delay circuit being applied as input (D) of the associated flip flop, whose output )Q) is applied on a corresponding input of the read register.

    6.
    发明专利
    未知

    公开(公告)号：FR2804521B1

    公开(公告)日：2002-04-05

    申请号：FR0001061

    申请日：2000-01-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： POMET ALAIN ,  MALHERBE ALEXANDRE ,  MARINET FABRICE

    IPC: G06F13/42 ,  G06K19/07 ,  G06F1/04 ,  H04L7/00 ,  H03L7/00

    Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

    8.
    发明专利
    未知

    公开(公告)号：DE602006011083D1

    公开(公告)日：2010-01-28

    申请号：DE602006011083

    申请日：2006-07-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： TEGLIA YANNICK ,  LIARDET PIERRE-YVAN ,  POMET ALAIN

    IPC: G06F11/00 ,  G06F21/75 ,  G06F21/77 ,  G07F7/10

    Abstract: The method involves triggering a temporary counter (TIMER), which counts a data account based on instructions following a main program (Pg), during an execution of instruction of the main program. An instruction of a secondary program, depending on the result of the main program, is executed if the counter reaches its account, where the result of the main program is an arithmetic result. An independent claim is also included for an integrated circuit for implementing a protection execution method.

    9.
    发明专利
    未知

    公开(公告)号：DE602005005002T2

    公开(公告)日：2008-08-28

    申请号：DE602005005002

    申请日：2005-01-05

    Applicant: AXALTO SA ,  ST MICROELECTRONICS SA

    Inventor： LEYDIER ROBERT ,  POMET ALAIN

    IPC: H04L7/033 ,  H04L7/00

    Abstract: A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization value (SV) is representative of a number of cycles of the oscillator signal (OS) contained within a time interval for a unit of external data. The synchronization value (SV) is an initial value (IV) during an initial synchronization phase and a measured value (MV) during a measurement-based synchronization phase. A control circuit (IFC) carries out a calibration step in which the initial value (IV) is a preprogrammed reset value (RV) and in which the measured value (MV) is stored as a calibration value (CV). The control circuit (IFC) applies the calibration value (CV) as the initial value (IV) in subsequent initial synchronization phases.

    10.
    发明专利
    未知

    公开(公告)号：DE60030074T2

    公开(公告)日：2007-03-29

    申请号：DE60030074

    申请日：2000-11-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： POMET ALAIN ,  PLESSIER BERNARD ,  SOURGEN LAURENT

    IPC: H04L9/08 ,  H04L9/20 ,  H04L9/00 ,  H04L9/10

    Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

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