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    41.
    发明专利
    未知

    公开(公告)号：DE60114651T2

    公开(公告)日：2006-06-01

    申请号：DE60114651

    申请日：2001-12-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BATTIATO SEBASTIANO ,  MANCUSO MASSIMO

    IPC: H04N7/30 ,  H04N7/26

    Abstract: A method of compressing digital images acquired in CFA (colour filter array) format (3) that utilizes optimised quantization matrices. The method, basing itself on the statistical characterization of the error introduced during the processing phase (4,5) that precedes compression (6), appropriately modifies the coefficients of any initial quantization matrix, even of a standard type, obtaining a greater compression efficiency without introducing further quality losses.

    42.
    发明专利
    未知

    公开(公告)号：DE60114651D1

    公开(公告)日：2005-12-08

    申请号：DE60114651

    申请日：2001-12-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BATTIATO SEBASTIANO ,  MANCUSO MASSIMO

    IPC: H04N7/26 ,  H04N7/30

    Abstract: A method of compressing digital images acquired in CFA (colour filter array) format (3) that utilizes optimised quantization matrices. The method, basing itself on the statistical characterization of the error introduced during the processing phase (4,5) that precedes compression (6), appropriately modifies the coefficients of any initial quantization matrix, even of a standard type, obtaining a greater compression efficiency without introducing further quality losses.

    43.
    发明专利
    未知

    公开(公告)号：DE69433225D1

    公开(公告)日：2003-11-13

    申请号：DE69433225

    申请日：1994-04-27

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： MANCUSO MASSIMO ,  POLUZZI RINALDO ,  RIZZOTTO GIANGUIDO

    IPC: H04N5/92 ,  H04N5/44 ,  H04N9/80 ,  H04N11/20 ,  H04N1/00

    Abstract: A television signal scanning conversion device of the type comprising at least one filtering block (3) having a plurality of digital inputs (Pi, X) which receive through an interface (2) components (X, Pi) of an interlaced television signal comprises also at least one calculation block (CALC1) connected to the signal inputs and operating with fuzzy logic. Said calculation block is capable of executing a switch between at least two different interpolation procedures, to wit interfield and intrafield.

    44.
    发明专利
    未知

    公开(公告)号：DE69530566D1

    公开(公告)日：2003-06-05

    申请号：DE69530566

    申请日：1995-01-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MANCUSO MASSIMO ,  MORETTI PAOLO ,  POLUZZI RINALDO ,  RIZZOTTO GIANGUIDO

    IPC: G06T7/60 ,  G06K9/46

    Abstract: A fuzzy method for the recognition of geometric shapes in images, the particularity whereof is that it comprises the following steps: recognition of at least one edge of a curve of an image; recognition of the gradient of the edge; correction of the gradient by virtue of first fuzzy means; and determination of the number of points that belong to the curve by virtue of second fuzzy means. The process according to the present invention is performed by a fuzzy device for the recognition of geometric shapes in images that comprises: an edge detector, adapted to recognize at least one edge of a curve of an image and adapted to recognize the gradient of the edge; a fuzzy gradient corrector, adapted to correct said gradient; a fuzzy vote attributor, adapted to determine the number of points that belong to the curve.

    45.
    发明专利
    未知

    公开(公告)号：DE69623253D1

    公开(公告)日：2002-10-02

    申请号：DE69623253

    申请日：1996-03-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MANCUSO MASSIMO ,  POLUZZI RINALDO

    IPC: G06T5/20 ,  H04N5/14 ,  H04N5/213 ,  H04N5/21

    Abstract: A processing device for video signals comprising: a memory device (1) suitable to store discrete image elements of a video field; a filtering device (3) supplied by the memory device and suitable to recover errors introduced by the memory device. The filtering device (3) comprises: a filter (4) having an input supplied with digital signals representative of values of a plurality of discrete image elements (P1...P8,X) comprising an image element (X) to be examined and neighbouring image elements (P1...P8), the discrete image elements being stored in the memory device (1), and an output supplying digital signals (CO) representative of a filtered value of the image element to be examined (X); noise detector means (5) operating on fuzzy-logic rules having an input supplied with the digital signals representative of the plurality of values of the image elements (P1...P8,X) and an output supplying a weight signal (K) representative of a degree of erroneousness of the discrete image element to be examined (X), the noise detector circuit (5) determining the degree of erroneousness comparing the value of the image element to be examined (X) with the values of the neighbouring image elements (P1...P8); soft-switch means (7) having a first input supplied with the digital signals representative of the value of the image element to be examined (X), a second input supplied with the output (CO) of the filter (4), a third input supplied with the weight signal (K), and an output supplying digital signals (O) representative of a weighted average of the output of the filter (CO) and of the digital signals representative of the value of the image element to be examined (X) according to respective weights determined by the degree of erroneousness.

    48.
    发明专利
    未知

    公开(公告)号：DE69605018T2

    公开(公告)日：2000-06-08

    申请号：DE69605018

    申请日：1996-02-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARQUES PEREIRA RICARDO ALBERT ,  MANCUSO MASSIMO ,  POLUZZI RINALDO

    IPC: H04N5/208 ,  G06T5/20 ,  G06T7/60 ,  H03H17/00 ,  H04N5/44 ,  H04N7/01

    Abstract: An interpolation filter for video signals comprises: first circuit means (R1-R3,L1-L3,C,7-9) supplied by discrete image elements (p1-p10) for detecting an image edge; second circuit means (10) supplied by the first circuit means for generating a first signal (DDA) corresponding to an average of the discrete image elements (p1-p10) along a direction of the image edge; third circuit means (11,12,13) supplied by the first circuit means for detecting a texture image area wherein an image edge cannot be univocally determined and for generating a second signal (K) depending on a degree of existance of the image edge; fourth circuit means (14), supplied by the first signal (DDA), the second signal (K) and a third signal (Mout), for generating an output signal (SWout) obtained by combining the first signal (DDA) with the third signal (Mout) in a proportion determined by the second signal (K), and multiplexing means (15) controlled by a control signal (CNT) for selectively coupling the third signal (Mout) to fourth signal (A), corresponding to an average of the discrete image elements (p1-p10) along a prescribed direction, or to a fifth signal (PF) corresponding to a previously received image element value.

    49.
    发明专利
    未知

    公开(公告)号：DE69421377D1

    公开(公告)日：1999-12-02

    申请号：DE69421377

    申请日：1994-02-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MANCUSO MASSIMO ,  POLUZZI RINALDO ,  RIZZOTTO GIANGUIDO

    IPC: H04N5/21 ,  G06T5/20 ,  H03H21/00 ,  H04N1/409

    Abstract: Filter achieving noise reduction and digital signal image edge exaltation comprising first and second noise reduction circuit means 2 and 3 designed to elect an image edge. Said first and second noise reduction circuit means 2 and 3 comprise each a first and second comparison element (S1,S2,S3,S4) whose input terminals are designed to receive separate digital signals of an image and an inferential circuit (C1,C2) connected to said comparison elements. Each inferential circuit (C1,C2) comprises a fuzzy logic unit designed to define activation levels (Vi) dependent upon signals generated by the comparison elements. The filter (1) comprises also a noise detection circuit (4) and an image edge detection circuit (6) both connected to the noise reduction circuit means (2,3) and designed to perform operations in accordance with fuzzy logic rules on the basis of activation levels (Vi) defined in the inferential circuits (C1,C2). The filter 1 also includes a noise reduction circuit (5) connected to the noise detection circuit (6) and designed to filter the digital image signals on the basis of the operations performed by the circuit (4). In the filter (1) is also included an image edge exalting circuit (7) connected to the noise reduction circuit (5) and to the image edge detection circuit (4) designed to perform on filtered digital image signals an image edge exaltation on the basis of the operations performed by the image edge detection circuit (6).

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