公开(公告)号：EP1047078B1

公开(公告)日：2006-08-09

申请号：EP99830235.0

申请日：1999-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： Gomiero, Enrico ,  Pio, Federico ,  Zuliani, Paola

IPC: G11C16/30 ,  G11C16/12

CPC classification number: G11C16/12 ,  G11C16/0433 ,  G11C16/30

公开(公告)号：EP1227499B1

公开(公告)日：2006-05-10

申请号：EP01830039.2

申请日：2001-01-24

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Gomiero, Enrico

IPC: G11C16/08 ,  G11C7/18

CPC classification number: G11C16/08 ,  G11C7/18

公开(公告)号：EP1501130A1

公开(公告)日：2005-01-26

申请号：EP03425483.9

申请日：2003-07-21

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Gomiero, Enrico

IPC: H01L29/423 ,  H01L21/28

CPC classification number: H01L29/4238 ,  H01L21/28123

Abstract: A MOS semiconductor device comprising an active area (1) of semiconductor material is described. The active area (1) comprises a central part (10) and an edge (9) having a inclined surface with respect to the central part (10). The MOS device comprises a gate finger (2) placed over of the central part (10) of said active area and formed by an insulating material layer (11) adjacent to the active area (1) and a conductive material layer (20) over said insulating material layer (11). The MOS device comprises at least one first pair of prolongations (51, 61, 71, 72) of said gate finger (2) which derive from both its opposite sides (49) transversal to the formation of the channel under the gate finger (2) and which fmd in a direction substantially parallel to the formation of said channel. Said first pair of prolongations (51, 61, 71, 72) are placed over portions (48) of the edge (9) of the active area (1) which are parallel to the formation of said channel and over their adjacent portions (21) of the central part of the active area (1).

Abstract translation: 描述了包括半导体材料的有源区（1）的MOS半导体器件。 有源区域（1）包括中心部分（10）和相对于中心部分（10）具有倾斜表面的边缘（9）。 MOS器件包括放置在所述有源区的中心部分（10）上的栅极指（2），并由邻近有源区（1）的绝缘材料层（11）和导电材料层（20）形成 所述绝缘材料层（11）。 所述MOS器件包括所述栅极指（2）的至少一个第一对延伸部（51,61,71,72），所述第二对延伸部​​从所述栅极指（2）的下方形成沟槽的相对侧（49） ），并且在基本上平行于所述通道的形成的方向上fmd。 所述第一对延长部分（51,61,71,72）放置在有源区域（1）的边缘（9）的与所述通道的形成平行并且在其相邻部分（21）上的部分（48） ）活动区域（1）的中心部分。

公开(公告)号：EP1079395B1

公开(公告)日：2003-12-03

申请号：EP99830478.6

申请日：1999-07-26

Applicant: STMicroelectronics S.r.l.

Inventor： Gomiero, Enrico ,  Pio, Federico

IPC: G11C16/10

CPC classification number: G11C16/12

公开(公告)号：EP1227499A1

公开(公告)日：2002-07-31

申请号：EP01830039.2

申请日：2001-01-24

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Gomiero, Enrico

IPC: G11C16/08 ,  G11C7/18

CPC classification number: G11C16/08 ,  G11C7/18

Abstract: Non-volatile, electrically alterable semiconductor memory, comprising at least one two-dimensional array of memory cells with a plurality of rows (R0-R511) and a plurality of columns (C(0;0)-C(127;31)), column selection means (CADD,3;CADD,10,INT_CADD,3) for selecting columns among said plurality of columns, and a write circuit (7) for simultaneously writing a first number of memory cells. A plurality of doped semiconductor regions (40-4127) is provided, extending transversally to the rows and subdividing a set of memory cells of each row in a corresponding plurality of subsets of memory cells, each subset of memory cells including memory cells of the row formed in a respective doped semiconductor region distinct from the remaining doped semiconductor regions and defining an elementary memory block (P) that can be individually erased. The plurality of doped semiconductor regions define a plurality of column packets (C(0;0)-C(0;31),...,C(127;0)-C(127;31)) each one containing a second number of columns equal to or higher than said first number, memory cells (MC) belonging to columns of a same column packet being formed in a same doped semiconductor region distinct from the doped semiconductor regions in which memory cells belonging to columns of the other column packets are formed. The column selection means are such that within each column packet columns containing memory cells that can be written simultaneously by the write circuit are distributed among the columns of the column packet so as to be at the substantially maximum distance from each other allowable within the column packet.

Abstract translation: 包括具有多行（R0-R511）和多列（C（0; 0）-C（127; 31））的存储器单元的至少一个二维阵列的非易失性，电可更改的半导体存储器， 用于选择所述多个列中的列的列选择装置（CADD，3; CADD，10，INT_CADD，3）和用于同时写入第一数量的存储单元的写电路（7）。 提供了多个掺杂半导体区域（40-4127），其横向延伸到行并且在对应的多个存储器单元子集中细分每一行的一组存储器单元，每个存储单元子集包括行的存储单元 形成在与剩余的掺杂半导体区域不同的相应的掺杂半导体区域中，并且限定可被单独擦除的基本存储块（P）。 多个掺杂半导体区域限定多个列分组（C（0; 0）-C（0; 31），...，C（127; 0）-C（127; 31）） 等于或高于所述第一数量的列数，属于相同列分组的列的存储单元（MC）形成在与掺杂半导体区域不同的掺杂半导体区域中，其中属于另一列的列的存储单元 数据包被形成。 列选择装置使得在每列列中，包含可由写电路同时写入的存储单元的列被分布在列分组的列之间，以便在列分组内可允许的彼此基本上最大距离 。

公开(公告)号：EP0612108B1

公开(公告)日：2001-07-04

申请号：EP93830062.1

申请日：1993-02-19

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Riva, Carlo

IPC: H01L27/115 ,  H01L29/788 ,  G11C16/04

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

公开(公告)号：EP1020907A1

公开(公告)日：2000-07-19

申请号：EP99830007.3

申请日：1999-01-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Zuliani, Paola ,  Fratin, Lorenzo

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Chip Outline Band (COB) structure for an integrated circuit integrated in a semiconductor chip having a semiconductor substrate (1) of a first conductivity type and biased at a common reference potential (GND) of the integrated circuit, the COB structure comprising a substantially annular region (3;30) formed in the substrate (1) along a periphery thereof, and at least one annular conductor region (40,60) superimposed on and contacting the substantially annular region (3;30), characterized in that said substantially annular region (3;30) is electrically connected at said common reference potential (GND).

Abstract translation: 用于集成在具有第一导电类型的半导体衬底（1）并且被集成电路的公共参考电位（GND）偏置的半导体芯片中的集成电路的芯片轮廓带（COB）结构，所述COB结构包括大致环形 沿着其周边形成在所述基板（1）中的区域（3; 30）以及叠置在所述基本环形区域（3; 30）上并且接触所述大致环形区域（3; 30）的至少一个环形导体区域（40,60），其特征在于， 区域（3; 30）在所述公共参考电位（GND）处电连接。

公开(公告)号：EP0989609A1

公开(公告)日：2000-03-29

申请号：EP98830562.9

申请日：1998-09-25

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/768 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The integrated device comprises, in combination: a first conductive region (6); a first insulating region (7) of dielectric material, covering the first conductive region; a first through region (15) of electrically conductive material, extending inside the first insulating region (7), and in direct electrical contact with the first conductive region (6); a second conductive region (10a), arranged above the first insulating region (7), in a position not aligned and not in contact with the first through region (15); a second insulating region (9) of dielectric material, covering the second conductive region (10a); a second through region (21) of electrically conductive material, extending inside the second insulating region (9) as far as the first through region (15), aligned and in direct electrical contact with the first through region; and a third conductive region (11a), arranged above the second insulating region (9), aligned and in direct electrical contact with the second through region (21).

Abstract translation: 该集成装置组合包括：第一导电区域（6）; 介电材料的第一绝缘区域（7），覆盖所述第一导电区域; 导电材料的第一通过区域（15），在所述第一绝缘区域（7）内延伸，并与所述第一导电区域（6）直接电接触; 布置在所述第一绝缘区域（7）上方的第二导电区域（10a）处于未对齐并且不与所述第一穿透区域（15）接触的位置; 介电材料的第二绝缘区域（9），覆盖所述第二导电区域（10a）; 在所述第二绝缘区域（9）的内部延伸至所述第一贯穿区域（15）的第二贯穿区域（21），其与所述第一贯穿区域对准并直接电接触; 以及布置在所述第二绝缘区域（9）上方的第三导电区域（11a），所述第三导电区域与所述第二贯穿区域（21）直接电接触。

公开(公告)号：EP0987763A1

公开(公告)日：2000-03-22

申请号：EP98830535.5

申请日：1998-09-15

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico

IPC: H01L27/07

CPC classification number: H01L27/0727

Abstract: Semiconductor device comprising a semiconductor layer (1) of a first type of conductivity, a gate oxide layer (4) superimposed to the semiconductor layer (1), at least one polysilicon region (11; 31) superimposed to the gate oxide layer (4), a first (13) and a second doped region (8,10; 13) of a second type of conductivity in the semiconductor layer (1). The first (13) and second doped region (8,10; 13) being spaced-apart in order to form a channel region therebetween, under the polysilicon layer (11; 31), and the first doped region (13) extends under a contact opening (14) obtained in the gate oxide layer (4) in correspondence of the polysilicon layer (11; 31), so that the polysilicon layer (11; 31) is electrically connected with the first doped region (13) through the contact opening (14).

Abstract translation: 包括第一导电类型的半导体层（1），与半导体层（1）重叠的栅极氧化层（4），至少一个多晶硅区域（11; 31）叠加到栅极氧化物层 ），在半导体层（1）中具有第二导电类型的第一（13）和第二掺杂区（8,10; 13）。 第一掺杂区域（13）和第二掺杂区域（8,10; 13）在多晶硅层（11; 31）下方间隔开以形成沟槽区域，并且第一掺杂区域 在所述栅极氧化物层（4）中获得的对应于所述多晶硅层（11; 31）的接触开口（14），使得所述多晶硅层（11; 31）通过所述触点与所述第一掺杂区域（13）电连接 开（14）。

公开(公告)号：EP0962982A1

公开(公告)日：1999-12-08

申请号：EP98830343.4

申请日：1998-06-03

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: Byte-switch structure for electrically erasable and programmable non-volatile memories, comprising a MOS transistor (3) having a drain electrode coupled to a respective metal control gate line (CGL), a source electrode coupled to a respective polysilicon byte control line (CG) which is connected to control gate electrodes of all the memory cells of a same memory byte or word and is formed in an upper polysilicon layer, and a gate electrode coupled to a respective word line (WL), said source and drain electrodes of the MOS transistor being respectively a first (5,5') and a second (9,9') doped regions of a first conductivity type formed in a semiconductor layer (15) of a second conductivity type at opposite sides of said respective word line (WL), characterized in that said first and second doped regions (5,5',9,9') are formed under said respective metal control gate line (CGL), and in that said polysilicon byte control gate line (CG) insulatively extends under said metal control gate line (CGL) to overlap said first doped region (5,5'), and contacts said first doped region (5,5') through a respective contact opening (17) in an underlying stack formed by an interpoly dielectric layer (14), a lower polysilicon layer (11) and an oxide layer (16).

Abstract translation: 用于电可擦除和可编程非易失性存储器的字节开关结构，包括具有耦合到相应的金属控制栅极线（CGL）的漏极的MOS晶体管（3），耦合到相应多晶硅字节控制线（CG ），其连接到相同存储器字节或字的所有存储单元的控制栅电极，并形成在上多晶硅层中，并且栅电极耦合到相应字线（WL），所述源电极和漏电极 MOS晶体管分别是形成在所述相应字线的相对侧上的第二导电类型的半导体层（15）中的第一导电类型的第一（5,5'）和第二（9,9'）掺杂区域 WL），其特征在于，所述第一和第二掺杂区（5,5'，9,9'）形成在所述相应的金属控制栅极线（CGL）下，并且所述多晶硅字节控制栅极线（CG）绝对地延伸 在金属控制门下面 ne（CGL）与所述第一掺杂区域（5,5'）重叠，并且通过由互聚电介质层（14）形成的下层堆叠中的相应接触开口（17）与所述第一掺杂区域（5,5'）接触， ，下多晶硅层（11）和氧化物层（16）。