公开(公告)号：US12014991B2

公开(公告)日：2024-06-18

申请号：US17951474

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Keunwook Shin ,  Kibum Kim ,  Hyunmi Kim ,  Hyeonjin Shin ,  Sanghun Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/532 ,  H01L29/16

CPC classification number: H01L23/5386 ,  H01L23/53204 ,  H01L23/5329 ,  H01L24/19 ,  H01L29/1606

Abstract: An interconnect structure may include a graphene-metal barrier on a substrate and a conductive layer on the graphene-metal barrier. The graphene-metal barrier may include a plurality of graphene layers and metal particles on grain boundaries of each graphene layer between the plurality of graphene layers. The metal particles may be formed at a ratio of 1 atom % to 10 atom % with respect to carbon of the plurality of graphene layers.

公开(公告)号：US11978704B2

公开(公告)日：2024-05-07

申请号：US16933544

申请日：2020-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok Lee ,  Hyeonjin Shin ,  Seongjun Park ,  Donghyun Im ,  Hyun Park ,  Keunwook Shin ,  Jongmyeong Lee ,  Hanjin Lim

IPC: H01L23/532

CPC classification number: H01L23/53276 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Example embodiments relate to a wiring structure, a method of forming the same, and an electronic device employing the same. The wiring structure includes a first conductive material layer and a nanocrystalline graphene layer on the first conductive material layer in direct contact with the metal layer.

公开(公告)号：US20240047564A1

公开(公告)日：2024-02-08

申请号：US18321290

申请日：2023-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joungeun YOO ,  Changhyun Kim ,  Kyung-Eun Byun ,  Minsu Seol ,  Keunwook Shin ,  Eunkyu Lee

IPC: H01L29/76 ,  H01L29/24

CPC classification number: H01L29/7606 ,  H01L29/24

Abstract: A semiconductor device may include a channel layer including a two-dimensional (2D) semiconductor material, a gate insulating layer on a center portion of the channel layer, a gate electrode on the gate insulating layer, and a first conductive layer and a second conductive layer respectively contacting opposite sides of the channel layer. Each of the first and second conductive layers may include metal boride.

公开(公告)号：US20240014303A1

公开(公告)日：2024-01-11

申请号：US18153633

申请日：2023-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung KWON ,  Minsu Seol ,  Keunwook Shin ,  Minseok Yoo

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7606 ,  H01L29/24 ,  H01L29/41741 ,  H01L29/78642 ,  H01L29/78696 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/66969

Abstract: A semiconductor device includes a substrate including a gate electrode therein, a trench penetrating the gate electrode and arranged in the substrate, a gate insulating layer in the trench and an upper surface of the substrate, a channel layer on the gate insulating layer and including a two-dimensional (2D) semiconductor material, and a source electrode and a drain electrode, which are spaced apart from each other on the channel layer.

公开(公告)号：US11862704B2

公开(公告)日：2024-01-02

申请号：US18059660

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong Heo ,  Yunseong Lee ,  Sanghyun Jo ,  Keunwook Shin ,  Hyeonjin Shin

IPC: H01L23/00 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L29/513 ,  H01L21/0228 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02356 ,  H01L29/516

Abstract: Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp2 bonding structure.

公开(公告)号：US11217531B2

公开(公告)日：2022-01-04

申请号：US16884590

申请日：2020-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Byun ,  Keunwook Shin ,  Yonghoon Kim ,  Hyeonjin Shin ,  Hyunjae Song ,  Changseok Lee ,  Changhyun Kim ,  Yeonchoo Cho

IPC: H01L23/532

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

公开(公告)号：US11094538B2

公开(公告)日：2021-08-17

申请号：US16260403

申请日：2019-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook Shin ,  Changhyun Kim ,  Kaoru Yamamoto ,  Changseok Lee ,  Hyunjae Song ,  Eunkyu Lee ,  Kyung-Eun Byun ,  Hyeonjin Shin ,  Sungjoo An

IPC: H01L21/02 ,  H01L29/16

Abstract: Provided is a method of forming graphene. The method of forming graphene includes treating a surface of a substrate placed in a reaction chamber with plasma while applying a bias to the substrate, and growing graphene on the surface of the substrate by plasma enhanced chemical vapor deposition (PECVD).

公开(公告)号：US10971451B2

公开(公告)日：2021-04-06

申请号：US16215899

申请日：2018-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Byun ,  Keunwook Shin ,  Yonghoon Kim ,  Hyeonjin Shin ,  Hyunjae Song ,  Changseok Lee ,  Changhyun Kim ,  Yeonchoo Cho

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

公开(公告)号：US20200039827A1

公开(公告)日：2020-02-06

申请号：US16233513

申请日：2018-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alum JUNG ,  Keunwook Shin ,  Kyung-Eun Byun ,  Hyeonjin Shin ,  Hyunseok Lim ,  Seunggeol Nam ,  Hyunjae Song ,  Yeonchoo Cho

IPC: C01B32/186 ,  C23C16/26 ,  C23C16/505 ,  C23C16/511 ,  H01L21/02 ,  H01L29/16 ,  H01L29/06 ,  H01L29/04

Abstract: A method of forming nanocrystalline graphene by a plasma-enhanced chemical vapor deposition process is provided. The method of forming nanocrystalline graphene includes arranging a protective layer on a substrate and growing nanocrystalline graphene directly on the protective layer by using a plasma of a reaction gas. The reaction gas may include a mixed gas of a carbon source gas, an inert gas, and hydrogen gas.

公开(公告)号：US10134628B2

公开(公告)日：2018-11-20

申请号：US15172908

申请日：2016-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae Song ,  Seunggeol Nam ,  Seongjun Park ,  Keunwook Shin ,  Hyeonjin Shin ,  Jaeho Lee ,  Changseok Lee ,  Yeonchoo Cho

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L21/285 ,  H01L29/45

Abstract: A multilayer structure includes a first material layer, a second material layer, and a diffusion barrier layer. The second material layer is connected to the first material layer. The second material layer is spaced apart from the first material layer. The diffusion barrier layer is between the first material layer and the second material layer. The diffusion barrier layer may include a two-dimensional (2D) material. The 2D material may be a non-graphene-based material, such as a metal chalcogenide-based material having a 2D crystal structure. The first material layer may be a semiconductor or an insulator, and the second material layer may be a conductor. At least a part of the multilayer structure may constitute an interconnection for an electronic device.