公开(公告)号：EP3572291A1

公开(公告)日：2019-11-27

申请号：EP18757476.9

申请日：2018-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： HAN, Kwanghoon ,  LEE, Kiseok ,  LEE, Janghee ,  JO, Sungmin ,  YANG, Ho ,  LEE, Myounghwan

IPC: B60R25/10 ,  B60R25/01 ,  H04L9/32

Abstract: The present disclosure relates to a communication technique and system thereof that fuses a 5G communication system with Internet of Things (loT) technology to support a higher data rate than a 4G system. The present disclosure may be applied to an intelligent service (for example, a smart home, a smart building, a smart city, a smart car or a connected car, a health care, a digital education, a retail, a security and safety related services, etc.) on the basis of 5G communication technology and loT related technology. The present disclosure relates to a technology for a Sensor Network, a Machine to Machine (M2M), a Machine Type Communication (MTC) and an Internet of Things (loT). The present disclosure may be utilized in the intelligent service (a smart home, a smart building, a smart city, a smart car or a connected car, a health care, a digital education, a retail, a security and safety related service, etc.) on the basis of the above technology. A key authentication method of an apparatus according to one embodiment of the present invention may comprise the steps of: receiving a signal from a terminal using a plurality of communication modules; determining whether the terminal is within a predetermined distance from the apparatus, on the basis of each signal received via the plurality of communication modules; and changing a control mode of a vehicle on which the apparatus is mounted, on the basis of whether the terminal is within the predetermined distance from the apparatus.

公开(公告)号：EP3534401A2

公开(公告)日：2019-09-04

申请号：EP19155115.9

申请日：2019-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  KIM, Bong-Soo ,  KIM, Jiyoung ,  KIM, Hui-Jung ,  PARK, Seokhan ,  LEE, Hunkook ,  HWANG, Yoosang

IPC: H01L27/108

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.