公开(公告)号：EP3534401A2

公开(公告)日：2019-09-04

申请号：EP19155115.9

申请日：2019-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  KIM, Bong-Soo ,  KIM, Jiyoung ,  KIM, Hui-Jung ,  PARK, Seokhan ,  LEE, Hunkook ,  HWANG, Yoosang

IPC: H01L27/108

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

公开(公告)号：EP3534401A3

公开(公告)日：2020-01-08

申请号：EP19155115.9

申请日：2019-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  KIM, Bong-Soo ,  KIM, Jiyoung ,  KIM, Hui-Jung ,  PARK, Seokhan ,  LEE, Hunkook ,  HWANG, Yoosang

IPC: H01L27/108 ,  H01L49/02

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.