公开(公告)号：EP3534401A2

公开(公告)日：2019-09-04

申请号：EP19155115.9

申请日：2019-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  KIM, Bong-Soo ,  KIM, Jiyoung ,  KIM, Hui-Jung ,  PARK, Seokhan ,  LEE, Hunkook ,  HWANG, Yoosang

IPC: H01L27/108

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

公开(公告)号：EP3968376A1

公开(公告)日：2022-03-16

申请号：EP21176527.6

申请日：2021-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： KIM, Hyosub ,  KIM, Keunnam ,  KIM, Manbok ,  KIM, Soojeong ,  PARK, Chulkwon ,  JEON, Seungbae ,  HWANG, Yoosang

IPC: H01L27/108

Abstract: Semiconductor devices may include an active pattern, a gate structure in an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure on a lower portion of a sidewall of the bit line structure, and an upper spacer structure on an upper portion of the sidewall of the bit line structure. The lower spacer structure includes first and second lower spacers sequentially stacked, the first lower spacer contacts the lower portion of the sidewall of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from the first lower spacer. A portion of the upper spacer structure contacting the upper portion of the sidewall of the bit line structure includes a material different from the first lower spacer.

公开(公告)号：EP4167700A1

公开(公告)日：2023-04-19

申请号：EP22189088.2

申请日：2022-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： KIM, Hyo-Sub ,  AHN, Junhyeok ,  LEE, Myeong-Dong ,  KIM, Hui-Jung ,  LEE, Kiseok ,  LEE, Jihun ,  HWANG, Yoosang

IPC: H10B12/00

Abstract: A semiconductor memory device and a method of fabricating a semiconductor memory device, the device including a first impurity region in a substrate; a first bit line that crosses over the substrate and is connected to the first impurity region; a bit-line contact between the first bit line and the first impurity region; and a contact ohmic layer between the bit-line contact and the first impurity region, wherein a width of a bottom surface of the bit-line contact is greater than a width of a bottom surface of the contact ohmic layer.

公开(公告)号：EP3534401A3

公开(公告)日：2020-01-08

申请号：EP19155115.9

申请日：2019-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： LEE, Kiseok ,  KIM, Bong-Soo ,  KIM, Jiyoung ,  KIM, Hui-Jung ,  PARK, Seokhan ,  LEE, Hunkook ,  HWANG, Yoosang

IPC: H01L27/108 ,  H01L49/02

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.