公开(公告)号：US20190019675A1

公开(公告)日：2019-01-17

申请号：US15874226

申请日：2018-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongwook LEE ,  Sangwon KIM ,  Minsu SEOL ,  Seongjun PARK ,  Hyeonjin SHIN ,  Yunseong LEE ,  Seongjun JEONG ,  Alum JUNG

IPC: H01L21/033 ,  H01L21/311 ,  C01B32/194

Abstract: Provided are a hardmask composition, a method of preparing the same, and a method of forming a patterned layer using the hardmask composition. The hardmask composition may include graphene quantum dots, a metal compound, and a solvent. The metal compound may be chemically bonded (e.g., covalently bonded) to the graphene quantum dots. The metal compound may include a metal oxide. The metal oxide may include at least one of zirconium (Zr) oxide, titanium (Ti) oxide, tungsten (W) oxide, or aluminum (Al) oxide. The graphene quantum dots may be bonded to the metal compound by an M-O—C bond or an M-C bond, where M is a metal element, O is oxygen, and C is carbon.

公开(公告)号：US20250142835A1

公开(公告)日：2025-05-01

申请号：US18927200

申请日：2024-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong LEE ,  Sijung YOO ,  Seunggeol NAM ,  Kihong KIM ,  Yoonsang PARK ,  Sanghyun JO

IPC: H10B51/30 ,  H10B51/20

Abstract: A semiconductor device, a memory device, and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a semiconductor substrate, a ferroelectric layer provided on the semiconductor substrate, an aluminum oxide layer provided on the ferroelectric layer, and a gate electrode provided on the aluminum oxide layer, wherein the aluminum oxide layer includes aluminum, oxygen, and hydrogen, and wherein a content of oxygen in the aluminum oxide layer is more than about 1.5 times and about 2 times or less a content of aluminum in the aluminum oxide layer.

公开(公告)号：US20240244848A1

公开(公告)日：2024-07-18

申请号：US18412793

申请日：2024-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae LEE ,  Jinseong HEO ,  Seunggeol NAM ,  Yunseong LEE ,  Dukhyun CHOE

IPC: H10B51/30 ,  H10B51/20

CPC classification number: H10B51/30 ,  H10B51/20

Abstract: Provided is a semiconductor device including a ferroelectric layer. The semiconductor device includes a channel layer including an n-type oxide semiconductor layer and a p-type oxide semiconductor layer, a ferroelectric layer disposed on the channel layer, a gate electrode disposed on the ferroelectric layer, and a reduced layer disposed on the channel layer and including an element having greater reducing power than a metal included in the channel layer.

公开(公告)号：US20240213349A1

公开(公告)日：2024-06-27

申请号：US18396258

申请日：2023-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun JO ,  Yunseong LEE ,  Hyangsook LEE ,  Dukhyun CHOE ,  Jinseong HEO

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78 ,  H10B51/20 ,  H10B53/20

CPC classification number: H01L29/516 ,  H01L29/40111 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/7851 ,  H10B51/20 ,  H10B53/20

Abstract: An electronic device and an electronic apparatus including the electronic device are provided. The electronic device includes a conductive material layer, and a ferroelectric layer covering the conductive material layer. The ferroelectric layer includes a first oxide layer including a first component, and a second oxide layer including hafnium and a second component and having a thickness that is twice or more than a thickness of the first oxide layer.

公开(公告)号：US20240081080A1

公开(公告)日：2024-03-07

申请号：US18461266

申请日：2023-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae LEE ,  Jinseong HEO ,  Seunggeol NAM ,  Yunseong LEE ,  Dukhyun CHOE

IPC: H10B51/20

CPC classification number: H10B51/20

Abstract: A semiconductor device including a substrate, an interfacial layer on the substrate, a ferroelectric layer on the interfacial layer, a gate on the ferroelectric layer, and the nitride protective layer between the interfacial layer and the gate and being adjacent to the ferroelectric layer.

公开(公告)号：US20230155026A1

公开(公告)日：2023-05-18

申请号：US17986237

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hagyoul BAE ,  Dukhyun CHOE ,  Jinseong HEO ,  Yunseong LEE ,  Seunggeol NAM ,  Hyunjae LEE

IPC: H01L29/78 ,  H01L27/108 ,  H01L27/24 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L27/10805 ,  H01L27/2436 ,  H01L29/516 ,  H01L29/7833 ,  H01L29/6684

Abstract: Provided are a semiconductor device and a semiconductor apparatus including the semiconductor device. The semiconductor device includes a substrate having a channel layer comprising a dopant, a ferroelectric layer on the channel layer; and a gate on the ferroelectric layer. The channel layer has a doping concentration of 1×1015 cm−3 to 1×1021 cm−3.

公开(公告)号：US20230116309A1

公开(公告)日：2023-04-13

申请号：US18060140

申请日：2022-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Sangwook KIM ,  Yunseong LEE ,  Sanghyun JO ,  Hyangsook LEE

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/51

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

公开(公告)号：US20230100991A1

公开(公告)日：2023-03-30

申请号：US18060372

申请日：2022-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Sangwook KIM ,  Yunseong LEE ,  Sanghyun JO

IPC: H01L29/78 ,  H01L21/28 ,  G11C11/22 ,  H01L29/66

Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

公开(公告)号：US20230068904A1

公开(公告)日：2023-03-02

申请号：US17876979

申请日：2022-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Yunseong LEE ,  Hyangsook LEE ,  Sanghyun JO ,  Seunggeol NAM ,  Taehwan MOON ,  Hagyoul BAE ,  Eunha LEE ,  Junho LEE

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/10

Abstract: An electronic device includes: a substrate including a source, a drain, and a channel between the source and the drain; a gate electrode arranged above the substrate and facing the channel, the gate electrode being apart from the channel in a first direction; and a ferroelectric thin film structure between the channel and the gate electrode, the ferroelectric thin film structure including a first ferroelectric layer, a crystallization barrier layer including a dielectric material, and a second ferroelectric layer, which are sequentially arranged from the channel in the first direction. The average of sizes of crystal grains of the first ferroelectric layer may be less than or equal to the average of sizes of crystal grains of the second ferroelectric layer, and owing to small crystal grains, dispersion of performance may be improved.

公开(公告)号：US20230068706A1

公开(公告)日：2023-03-02

申请号：US17896481

申请日：2022-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hagyoul BAE ,  Jinseong HEO ,  Seunggeol NAM ,  Taehwan MOON ,  Yunseong LEE

IPC: H01L27/24 ,  H01L27/11582 ,  H01L27/11597

Abstract: A non-volatile memory device is provided. The nonvolatile memory device includes a metal pillar, a channel layer separated from the metal pillar and surrounding a side surface of the metal pillar, a source arranged on one end of the channel layer, a drain arranged on the other end of the channel layer, a gate insulating layer surrounding a side surface of the channel layer, and a plurality of insulating elements and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer and surrounding a side surface of the gate insulating layer.