公开(公告)号：US20190305172A1

公开(公告)日：2019-10-03

申请号：US16442990

申请日：2019-06-17

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur

IPC: H01L33/00 ,  H01L33/04 ,  H01L33/32 ,  H01L31/0352 ,  H01L33/14 ,  H01L31/105 ,  H01L31/0224 ,  H01L31/0304 ,  H01L33/02 ,  H01L31/109

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.

公开(公告)号：US10297460B2

公开(公告)日：2019-05-21

申请号：US15496887

申请日：2017-04-25

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Jinwei Yang ,  Wenhong Sun ,  Rakesh Jain ,  Michael Shur ,  Remigijus Gaska

IPC: H01L29/15 ,  H01L31/0256 ,  H01L21/308 ,  H01L29/66 ,  H01L21/02 ,  H01L33/12 ,  H01L29/20 ,  H01L33/00

Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

公开(公告)号：US20180248071A1

公开(公告)日：2018-08-30

申请号：US15966022

申请日：2018-04-30

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur

IPC: H01L33/00 ,  H01L31/105 ,  H01L31/0352 ,  H01L31/0224 ,  H01L33/04 ,  H01L33/14

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.

公开(公告)号：US20180108806A1

公开(公告)日：2018-04-19

申请号：US15857853

申请日：2017-12-29

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/06 ,  H01L21/02 ,  H01L29/778 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32

CPC classification number: H01L33/06 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0688 ,  H01L29/2003 ,  H01L29/518 ,  H01L29/7786 ,  H01L33/007 ,  H01L33/12 ,  H01L33/20 ,  H01L33/22 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0083 ,  H01L2933/0091

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

公开(公告)号：US09923117B2

公开(公告)日：2018-03-20

申请号：US14984156

申请日：2015-12-30

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Alexander Dobrinsky ,  Alexander Lunev ,  Rakesh Jain ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/32 ,  H01L33/10 ,  H01L33/00 ,  H01L33/12 ,  H01L33/46

CPC classification number: H01L33/10 ,  H01L33/007 ,  H01L33/12 ,  H01L33/32 ,  H01L33/46

Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher. In one embodiment, the semiconductor layer is used to form an optoelectronic device.

公开(公告)号：US09799793B2

公开(公告)日：2017-10-24

申请号：US15391948

申请日：2016-12-28

Applicant: Sensor Electronic Technology, Inc.

Inventor： Daniel Billingsley ,  Robert M. Kennedy ,  Wenhong Sun ,  Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L29/06 ,  H01L33/00 ,  H01L33/32 ,  H01L33/12 ,  H01L29/778 ,  H01L29/66 ,  H01L33/20 ,  H01L33/24

CPC classification number: H01L33/0025 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/12 ,  H01L33/20 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225

Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

公开(公告)号：US20170229611A1

公开(公告)日：2017-08-10

申请号：US15496887

申请日：2017-04-25

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Jinwei Yang ,  Wenhong Sun ,  Rakesh Jain ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/12 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/308 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/158 ,  H01L29/2003 ,  H01L29/66075 ,  H01L33/007 ,  H01L33/12

Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

公开(公告)号：US09680061B2

公开(公告)日：2017-06-13

申请号：US15212659

申请日：2016-07-18

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur

IPC: H01L27/15 ,  H01L31/072 ,  H01L33/22 ,  H01L33/12 ,  H01L33/32 ,  H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L29/34 ,  H01L29/778 ,  H01L33/24 ,  H01L29/205 ,  H01L33/00 ,  H01L33/06 ,  H01L33/10

CPC classification number: H01L33/22 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02658 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/06 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0091

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

公开(公告)号：US20160322535A1

公开(公告)日：2016-11-03

申请号：US15212659

申请日：2016-07-18

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  H01L33/12 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L33/06 ,  H01L33/10 ,  H01L21/02 ,  H01L33/00 ,  H01L33/32 ,  H01L29/34

CPC classification number: H01L33/22 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02658 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/06 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0091

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

公开(公告)号：US20160240739A1

公开(公告)日：2016-08-18

申请号：US15138415

申请日：2016-04-26

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Rakesh Jain ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  H01L33/06 ,  H01L33/12 ,  G06F17/50 ,  H01L33/00 ,  H01L33/32

CPC classification number: H01L33/22 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02617 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32 ,  H01L2224/16225

Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.

Abstract translation: 提供了用于改善半导体层的生长的图案化表面，例如III族氮化物基半导体层。 图案化表面可以包括一组基本平坦的顶表面和多个开口。 每个基本上平坦的顶表面可以具有小于约0.5纳米的均方根粗糙度，并且开口可以具有在约0.1微米和5微米之间的特征尺寸。 基本平坦的顶表面中的一个或多个可以基于目标辐射进行图案化。