公开(公告)号：WO1993010491A1

公开(公告)日：1993-05-27

申请号：PCT/US1992009908

申请日：1992-11-19

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  PETERSON, LuVerne, Ray ,  FLORA, Laurence, Paul

IPC: G06F07/50

CPC classification number: G06F7/506 ,  G06F2207/3876

Abstract: A digital adder module (M1) has a carry-in terminal (12), N pairs of data terminals (10 and 11), N sum terminals (S1-S4), and a carry-out terminal (16). A high-speed low-capacitance carry bypass signal path couples the carry-in terminal to the carry-out terminal. In one preferred embodiment, the capacitance of the bypass path is due solely to one transistor channel (T11) plus one transistor drain (T10) plus one internal logic gate (I1) plus interconnections between them.

公开(公告)号：WO1993006552A1

公开(公告)日：1993-04-01

申请号：PCT/US1992007884

申请日：1992-09-17

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  PETERSON, LuVerne, Ray ,  KUMBASAR, Cevat

IPC: G06F12/08

CPC classification number: G11C15/00 ,  G06F7/02 ,  G06F12/0895

Abstract: A random access compare array, on an integrated circuit chip is comprised of a plurality of multi-bit comparator circuits (10). Each comparator circuit is coupled to a respective multi-bit register (11); and, each comparator circuit is also coupled to an address distribution circuit (21-1 through 21-Y) which receives a compare address (AH) and sends the compare address to all of the comparator circuits. A respective match signal (M1,1 to MX,Y) is generated by each comparator circuit which indicates when the compare address and the content of the register that is coupled to the comparator are equal. Also, operating in parallel with the generation of the match signals is a match selection circuit (30, 31-1 through 31-X, 32, 33-1 through 33-Y, 34-1 through 34-Y, 35, 36) which receives a select address (ALR and ALC) and in response passes one match signal (M) to a single output pin (37). Due to the parallel operation of the compare-select circuits, the speed of operation is greatly increased; and due to the selective passing of any of the match signals to a single output pin, the size of the array is not pin limited.

公开(公告)号：WO1993000639A1

公开(公告)日：1993-01-07

申请号：PCT/US1992005079

申请日：1992-06-19

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  HO, Kin, M. ,  KURPANEK, Dietmar, M. ,  LI, Adam, W., K. ,  LIU, Jonathan, W. ,  SASSONE, Brian, J. ,  SHEIKH, Tahir, Q. ,  TAM, Sam

IPC: G06F13/12

CPC classification number: G06F13/122 ,  G06F12/0875

Abstract: A multiprocessor computer system wherein a base processor is coupled in asynchronous O-ring fashion to an associated input/output adapter, with the processor and I/O adapter each including associated private cache memory through which they are both connected with a common shared MP bus via a single connector channel.

Abstract translation: 一种多处理器计算机系统，其中基本处理器以异步O形环方式耦合到相关联的输入/输出适配器，处理器和I / O适配器各自包括相关联的专用高速缓冲存储器，它们都通过它们与公共共享MP总线 通过单个连接器通道。

公开(公告)号：WO1992018877A1

公开(公告)日：1992-10-29

申请号：PCT/US1992002748

申请日：1992-04-06

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  RUBIN, William, L. ,  LEYH, Carl, H.

IPC: G01S13/95

CPC classification number: G01S13/951 ,  Y02A90/18

Abstract: A microburst precursor detector samples radar returns from meteorological radar signal reflectors and processes the signal returns in a statistical manner to determine average radar reflectivity and to extract Doppler signal parameters. The vertical velocity in still air and the vertical velocity of the meteorological radar reflectors are respectively determined from the average reflectivity and the Doppler signal parameters. The difference between the two vertical velocities is taken to determine the vertical wind velocity. The vertical wind velocity and the average reflectivity are processed to predict the occurrence of a microburst.

公开(公告)号：WO1992010035A1

公开(公告)日：1992-06-11

申请号：PCT/US1991008878

申请日：1991-11-27

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  TEAGUE, Tommy, K.

IPC: H03M07/00

CPC classification number: H03M7/06 ,  G06F5/00

Abstract: Improved means and methods are provided for transmitting binary data on a communication system, such as E-mail, which restricts the number of acceptable characters that can be transmitted. In a preferred embodiment, the binary data to be transmitted is first subjected to a Welch compression and then converted into base-85 digits for transmission. At the receiving end, the received base-85 digits are converted back into compressed binary and then subjected to Welch decompression to obtain the original binary data.

公开(公告)号：WO1992009086A1

公开(公告)日：1992-05-29

申请号：PCT/US1991008580

申请日：1991-11-18

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  LEE, David, Chin-Chung ,  EASLEY, Jeffery, Lee ,  MALIK, Ashgar, Kamal

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C8/16

Abstract: An improved CAM (content addressable memory) cell is provided with dual address lines operable independently for a Read operation or for a Write operation. The cell is additionally provided with dual ports so that the first port permits a data input for Write operations or alternatively a data input Search-Compare operations. The second port (Data Output) is independently connected to enable a Read out of data residing in the cell. Each CAM cell also has a coincidence line (match-hit) output to indicate when an input Search bit or word coincides with resident data within the CAM cell. The CAM cells are arranged in an array of 'm' rows with each row having 'n' bits to hold a 'n' bit word. Operationally the CAM permits both 'Read' and 'Search-Compare' operations to be accomplished in one clock cycle rather than the usual requirement of 3-4 clock cycles.

公开(公告)号：WO1991007722A1

公开(公告)日：1991-05-30

申请号：PCT/US1990006855

申请日：1990-11-21

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  JEPPESEN, James, Henry, III ,  WHITTAKER, Bruce, Ernest

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: An expandable memory structure, both vertically and laterally, which uses a plurality of uniformly sized and duplicated chips which includes parity check functionality using an auxiliary parity memory chip of the same type and size. Selection circuitry permits choice of format for odd or even parity.

公开(公告)号：WO1990012373A1

公开(公告)日：1990-10-18

申请号：PCT/US1990001645

申请日：1990-03-28

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  RYAN, Robert, Thomas

IPC: G06K15/12

CPC classification number: G06K15/1276 ,  G06K15/128

Abstract: A high speed real time print head controller (Fig. 1) is provided for supporting a high resolution vector graphics command set which is employed to perform flexible high speed generation of textured line effects (Fig. 3). Rows of continuous graphics line information (84) are generated by a print head controller and modified by novel texture control means (25, 32, 39) and style control means (21) so that the bit information supplied to a shift alignment means (17) under control of the style logic means (21) is loaded into a bit map memory (11) one parallel word at a time to completely load a page of information in the bit map memory (11) in the desired style and textured pixel format for presentation to a write head buffer (14) for printout.

公开(公告)号：WO1990009640A1

公开(公告)日：1990-08-23

申请号：PCT/US1990000859

申请日：1990-02-15

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  CROZIER, George, W.

IPC: G06F15/62

CPC classification number: G06T3/606

Abstract: Apparatus (20) is provided for shifting the output of a bit matrix character generator (17) ninety degrees to provide ninety degree shifted characters and comprises a barrel shifter (28) for barrel shifting bit slices of the bit matrix characters coupled to a linear array shifter (Fig. 3) for linear array shifting the information that was first barrel shifted. A feedback loop (31-35) which includes a rotate RAM memory (34) having its output (35) connected to the input of the barrel shifter means (28) to twice barrel shift the information which was previously barrel shifted and then linear array shifted to provide a bit matrix character output (29) which is rotated ninety degrees from the original bit matrix character provided at the output of the character generator.

公开(公告)号：WO1990007756A1

公开(公告)日：1990-07-12

申请号：PCT/US1989005568

申请日：1989-12-08

Applicant: UNISYS CORPORATION ,  KERYHUEL, Alain

Inventor： UNISYS CORPORATION

IPC: G07F07/10

CPC classification number: G07F7/1008 ,  G06Q20/341 ,  G06Q20/346 ,  G07F7/0886 ,  G07F19/20 ,  G07F19/201 ,  G07F19/205 ,  G07F19/209 ,  G07F19/21

Abstract: A system provides a card (24) whereon a keyboard (72) is provided. The card (24) has contacts (80) on the rear thereof. The card (24) is brought into electrical contact with apparatus requiring use of a keyboard (72). Three embodiments are given, firstly, an automatic teller unit (10), secondly, a transfer terminal (188) for transferring funds between cards, and thirdly, a telephone (256). Each card (24) is provided with a money memory wherefrom numbers can be subracted in payment or whereto numbers may be added to effect payment to the card (24). Each card is capable of a validation process whereby numbers entered on the card keyboard (72) are compared with a secret number stored in an inaccessible read-only memory (78) and the results of comparison between the keyboard (72) entered sequence and the stored number provided to the outside apparatus. The card (24) is provided with a delay between successive instances of attempts to enter the personal identification number thereby to slow down the process of trial and error of discovery of a personal identification number.

Abstract translation: 一个系统提供了一个提供键盘（72）的卡（24）。 卡（24）的后部具有触点（80）。 卡（24）与需要使用键盘（72）的设备电接触。 给出三个实施例，首先是自动柜员机（10），其次是用于在卡之间转帐资金的转账终端（188），其次是电话机（256）。 每个卡（24）都设置有货币存储器，其中可以支付数字，或者可以添加数字以便对卡（24）进行支付。 每个卡都能够进行验证过程，其中输入到卡键盘（72）上的号码与存储在不可访问的只读存储器（78）中的密码进行比较，并且键盘（72）输入序列和 存储号码提供给外部设备。 卡（24）在连续尝试输入个人识别号码之间被提供延迟，从而减缓发现个人识别号码的尝试和错误的过程。