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    Dual damascene process for integrated circuits
    41.
    发明专利
    Dual damascene process for integrated circuits 未知

    公开(公告)号：DE19719909A1

    公开(公告)日：1998-11-19

    申请号：DE19719909

    申请日：1997-05-13

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YEW TRI-RUNG ,  LIU MONG-CHUNG ,  LUR WATER ,  SUN SHIH-WEI

    IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522

    Abstract: Making an integrated circuit with first (78) and second (76) level conductor structures comprises: (a) providing a substrate (50) with integrated circuit device(s); (b) providing an interlayer dielectric layer (52) over the substrate; (c) providing an etch stop layer (54) over it; (d) patterning the etch stop layer to define openings corresponding to positions where first level conductor structures are to be formed; (e) providing an intermetallic dielectric layer (58) over the patterned etch stop layer; (f) forming a second level mask over the intermetallic dielectric layer; this mask having openings corresponding to positions where second level conductor structures are to be formed; (g) etching through the openings in the second level mask to form second level conductor openings in the intermetallic dielectric layer; (h) etching through the openings in the patterned etch stop layer to form first level conductor openings in the interlayer dielectric layer; the edges of the openings have a tapered configuration; they provide for a step-free transition with the second level conductor openings; and (i) depositing metal into the first and second level conductor openings.

    Formation of interconnects in semiconductor device between different level wiring lines
    42.
    发明专利
    Formation of interconnects in semiconductor device between different level wiring lines 未知

    公开(公告)号：NL1005911C2

    公开(公告)日：1998-10-27

    申请号：NL1005911

    申请日：1997-04-25

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： SUN SHIH-WEI

    IPC: H01L21/768 ,  H01L23/522

    Abstract: Forming an interconnect in a semiconductor device comprises: (a) providing a conductive layer adjacent a first insulating layer above a semiconductor substrate; the two layers have coplanar upper surfaces; (b) depositing an etch stop layer, different from the first insulating layer, on the upper surfaces of the two layers; (c) depositing a second insulating layer, different from the etch stop layer, on the etch stop layer; (d) etching a via to expose a portion of the etch stop layer, the etched via is formed at least partially above the conductive layer; (e) removing the etch stop layer within the via; (f) depositing a glue layer on the conductive layer within the via; and (g) filling the via with a conductive material. Also claimed is a similar method of forming an interconnect comprising: providing an insulating layer (30) over a semiconductor substrate (10); forming a pattern of depressions in the insulating layer; depositing a metal layer over the insulating layer; planarising the metal layer to form a pattern of first level metal wiring lines (32) within the insulating layer corresponding to the pattern of depressions; depositing an etch stop layer (34) on surfaces of the insulating layer and the metal wiring lines; depositing a dielectric layer (36) over the etch stop layer; etching a via through the dielectric layer to expose the etch stop layer; removing the etch stop layer within the via to expose at least a portion of a metal wiring line; depositing a glue layer on the metal wiring line within the via; and forming a metal plug (42) within the via.

    Dram cells
    44.
    发明专利
    Dram cells 未知

    公开(公告)号：GB2318681A

    公开(公告)日：1998-04-29

    申请号：GB9622406

    申请日：1996-10-28

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： SUN SHIH-WEI

    IPC: H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12

    Abstract: A silicon on insulator (SOI) DRAM has a layer of buried oxide 12 covered by a thin layer of crystalline silicon on the surface of a bulk silicon substrate 10. Field oxide regions 14 are formed extending through the thin crystalline silicon surface layer and into contact with the buried oxide layer. Gate oxide layers, gate electrodes 18 and source/drain regions 24 for the transfer FETs of the DRAM are formed in and on the thin crystalline silicon surface layer in the active regions between the field oxide regions. A trench is opened through one of the source/drain regions of each of the transfer FETs. A layer of doped polysilicon is provided to line the trenches and is patterned to form at least a part of the bottom electrodes 32 of the charge storage capacitors for the DRAM. The bottom electrodes are covered with a thin dielectric layer 34 and an upper electrode 36 of doped polysilicon is provided. Preferably, the trench for the bottom capacitor electrode extends through the buried oxide layer and may extend into the bulk silicon.

    50.
    发明专利
    未知

    公开(公告)号：NL1010203C2

    公开(公告)日：2000-03-30

    申请号：NL1010203

    申请日：1998-09-28

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YEW TRI-RUNG ,  LUR WATER ,  SUN SHIH-WEI ,  HUANG YIMIN

    IPC: H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

    Abstract: A method for forming a barrier layer comprising the steps of first providing a semiconductor substrate that has a conductive layer already formed thereon. Then, a dielectric layer such as an organic low-k dielectric layer is deposited over the conductive layer and the semiconductor substrate. Next, an opening in formed in the dielectric layer exposing the conductive layer. Thereafter, a first barrier layer is deposited into the opening and the surrounding area. The first barrier layer can be a silicon-contained layer or a doped silicon (doped-Si) layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method, a low-pressure chemical vapor deposition (LPCVD) method, an electron beam evaporation method or a sputtering method. Finally, a second barrier layer is formed over the first barrier layer. The second barrier layer can be a titanium/titanium nitride (Ti/TiN) layer, a tungsten nitride (WN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer.

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