公开(公告)号：US10049929B2

公开(公告)日：2018-08-14

申请号：US15008453

申请日：2016-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Chieh-Te Chen

IPC: H01L21/4763 ,  H01L21/768 ,  H01L29/78 ,  H01L23/485 ,  H01L29/66 ,  H01L21/283 ,  H01L21/321 ,  H01L23/528 ,  H01L29/45 ,  H01L29/417 ,  H01L23/532 ,  H01L29/165

Abstract: The present invention provides a method of forming a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate.

公开(公告)号：US20180166441A1

公开(公告)日：2018-06-14

申请号：US15825057

申请日：2017-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Hsiang-Hung Peng ,  Wei-Hao Huang ,  Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L27/0629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L28/20 ,  H01L28/24

Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.

公开(公告)号：US20180068951A1

公开(公告)日：2018-03-08

申请号：US15285471

申请日：2016-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Chih-Sen Huang

IPC: H01L23/535 ,  H01L23/528 ,  H01L27/092 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/092 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is performed to remove part of the ILD layer for forming a recess, a second etching process is performed to remove part of the first spacer for expanding the recess, and a contact plug is formed in the recess.

公开(公告)号：US09780199B2

公开(公告)日：2017-10-03

申请号：US14862165

申请日：2015-09-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Shih-Fang Tzou

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a gate structure is formed on a substrate, and two source/drain regions are formed. Then, a contact etching stop layer (CESL) is formed to cover the source/drain regions, and a first interlayer dielectric (ILD) layer is formed on the CESL. Next, a replace metal gate process is performed to form a metal gate and a capping layer on the metal gate, and a second ILD layer is formed on the first ILD layer. Following these, a first opening is formed in the second and first ILD layers to partially expose the CESL, and a second opening is formed in the second ILD to expose the capping layer. Finally, the CESL and the capping layer are simultaneously removed.

公开(公告)号：US20170103896A1

公开(公告)日：2017-04-13

申请号：US15243986

申请日：2016-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Chun-Hsien Lin

IPC: H01L21/28 ,  H01L21/285 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/28123 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0653 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

公开(公告)号：US09613969B2

公开(公告)日：2017-04-04

申请号：US14793714

申请日：2015-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L27/11 ,  H01L29/76 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

公开(公告)号：US09607892B2

公开(公告)日：2017-03-28

申请号：US15201511

申请日：2016-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Yu-Cheng Tung

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/66 ,  H01L21/308 ,  H01L23/522 ,  H01L23/485 ,  H01L29/66 ,  H01L29/00

CPC classification number: H01L21/76895 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/3085 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/00 ,  H01L29/66545 ,  H01L29/66553

Abstract: A method for fabricating semiconductor device comprising: providing a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; removing part of the gate structure; forming a first mask layer on the first ILD layer and the gate structure; removing the first mask layer on the first ILD layer and part of the first mask layer on the gate structure for forming a first hard mask on the gate structure; forming a second mask layer on the first ILD layer, the first hard mask, and the gate structure; and planarizing the second mask layer to form a second hard mask on the gate structure, in which the top surfaces of the first hard mask, the second hard mask, and the first ILD layer are coplanar.

公开(公告)号：US09564371B2

公开(公告)日：2017-02-07

申请号：US14514374

申请日：2014-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Tsung-Hung Chang ,  Jia-Rong Wu ,  Ching-Ling Lin ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/823475 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823431

Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.

Abstract translation: 一种半导体器件的制造方法，其特征在于，首先，在基板上形成有基板，在所述散热片结构上形成有多个栅极结构，然后将硬掩模层和第一光致抗蚀剂层 形成在鳍结构上，然后在第一光致抗蚀剂层上进行第一蚀刻工艺，然后在剩余的第一光致抗蚀剂层和剩余的硬掩模层上形成多个图案化的光致抗蚀剂层，其中每个图案化的光致抗蚀剂层被设置 每个栅极结构的正上方，并且每个图案化的光致抗蚀剂的宽度大于每个栅极结构的宽度，并且图案化的光致抗蚀剂层用作硬掩模以执行第二蚀刻工艺以形成多个第二沟槽。

公开(公告)号：US20160351575A1

公开(公告)日：2016-12-01

申请号：US14793714

申请日：2015-07-07

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  Wei-Cyuan Lo ,  Ming-Jui Chen ,  Chia-Lin Lu ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Tan-Ya Yin ,  Chia-Wei Huang ,  Shu-Ru Wang ,  Yung-Feng Cheng

IPC: H01L27/11 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L21/823871 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/7851 ,  H01L29/7853

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

Abstract translation: 本发明提供一种半导体结构，其包括基板，多个翅片结构，多个栅极结构，电介质层和多个接触插塞。 衬底具有存储区域。 翅片结构设置在存储区域中的基板上，每个沿着第一方向延伸。 栅极结构设置在翅片结构上，每个翼结构沿着第二方向延伸。 电介质层设置在栅极结构和鳍结构上。 接触插头设置在电介质层中并电连接到鳍结构中的源极/漏极区域。 从顶部看，接触塞具有梯形或五边形。 本发明还提供了一种形成该方法的方法。

公开(公告)号：US20160064327A1

公开(公告)日：2016-03-03

申请号：US14494607

申请日：2014-09-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0629

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 基板上的第一金属栅极; 第一个金属门上的第一个硬掩模; 在第一金属栅极的顶部和周围的层间绝缘层（ILD）层; 以及嵌入ILD层中的图案化金属层，其中图案化金属层的顶表面比第一硬掩模的顶表面低。