公开(公告)号：US20020079490A1

公开(公告)日：2002-06-27

申请号：US09969792

申请日：2001-10-04

Applicant: Mitsubishi Denki Kabushiki Kaisha

Inventor： Shinichi Izuo ,  Hiroshi Ohji ,  Kazuhiko Tsutsumi

IPC: H01L023/58

CPC classification number: B81C1/00111 ,  B81B2201/0214 ,  B81C2201/0114 ,  B81C2201/0178 ,  G01N27/44791

Abstract: Providing a columnar structure having a uniform shape and excellent heat resistance and mechanical strength that is formed on a substrate of silicon, a method of preparing the structure, and a DNA separation device prepared by the method. A structure has, on a substrate made of silicon, columns of which main surface is covered with a thermally oxidized film. The columns are made of the thermally oxidized film only or of the thermally oxidized film and silicon. The thermally oxidized film formed on the columns is connected to those formed on the surface or inside of the substrate.

Abstract translation: 提供具有均匀形状的柱状结构，并且在硅衬底上形成的优异的耐热性和机械强度，制备该结构的方法以及通过该方法制备的DNA分离装置。 在由硅制成的基板上，在主表面被热氧化膜覆盖的列中， 柱仅由热氧化膜或热氧化膜和硅制成。 形成在列上的热氧化膜与在基板的表面或内部形成的热氧化膜连接。

公开(公告)号：US06342427B1

公开(公告)日：2002-01-29

申请号：US09473968

申请日：1999-12-29

Applicant: Chang Auck Choi ,  Chi Hoon Jun ,  Won Ick Jang ,  Yun Tae Kim

Inventor： Chang Auck Choi ,  Chi Hoon Jun ,  Won Ick Jang ,  Yun Tae Kim

IPC: H01L2100

CPC classification number: B81C1/00047 ,  B81B2203/033 ,  B81C2201/0133 ,  B81C2201/0178 ,  B81C2203/0136

Abstract: A method for forming a micro cavity is disclosed. In the method for forming the cavity, a first layer is formed on a silicon layer and a trench is formed in the silicon layer by selectively etching the silicon layer. A second and a third layers are formed on the trench and on the silicon layer. Etching holes are formed through the third layer by partially etching the third layer. A cavity is formed between the silicon layer and the third layer after the second layer is removed through the etching holes. Therefore, the cavity having a large size can be easily formed and sealed in the silicon layer by utilizing the volume expansion of the silicon or the poly silicon layer. Also, a vacuum micro cavity can be formed according as a low vacuum CVD oxide layer or a nitride layer formed on the etching holes which are partially opened after the thermal oxidation process by controlling the size of the etching holes concerning the other portion of the poly silicon layer.

Abstract translation: 公开了一种用于形成微腔的方法。 在形成空腔的方法中，在硅层上形成第一层，并且通过选择性地蚀刻硅层，在硅层中形成沟槽。 在沟槽和硅层上形成第二和第三层。 通过部分地蚀刻第三层，通过第三层形成蚀刻孔。 在通过蚀刻孔除去第二层之后，在硅层和第三层之间形成空穴。 因此，通过利用硅或多晶硅层的体积膨胀，可以容易地在硅层中形成并密封具有大尺寸的空腔。 此外，可以根据在热氧化处理后部分打开的蚀刻孔上形成的低真空CVD氧化物层或氮化物层，通过控制与聚合物的其它部分相关的蚀刻孔的尺寸，形成真空微腔 硅层。

公开(公告)号：US5736430A

公开(公告)日：1998-04-07

申请号：US480267

申请日：1995-06-07

Applicant: James D. Seefeldt ,  Michael F. Mattes

Inventor： James D. Seefeldt ,  Michael F. Mattes

IPC: G01L9/04 ,  B81B3/00 ,  G01L9/00 ,  G01P15/08 ,  G01P15/12 ,  H01L29/84 ,  H01L21/465

CPC classification number: B81C1/00158 ,  G01L9/0042 ,  G01L9/0055 ,  G01P15/0802 ,  G01P15/123 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0178 ,  Y10S438/96

Abstract: A method of forming apparatus including a force transducer on a silicon substrate having an upper surface, the silicon substrate including a dopant of one of the n-type or the p-type, the force transducer including a cavity having spaced side walls and a diaphragm supported in the cavity, the diaphragm extending between the side walls of the cavity, comprising the steps of: a. implant in the substrate a layer of a dopant of the one of the n-type or the p-type; b. deposit an epitaxial layer on the upper surface of the substrate, the epitaxial layer including a dopant of the other of the n-type or the p-type; c. implant spaced sinkers through the epitaxial layer and into electrical connection with the layer of a dopant of the one of the n-type or the p-type, each of the sinkers including a dopant of the one of the n-type or the p-type; d. anodize the substrate to form porous silicon of the sinkers and the layer; e. oxidize the porous silicon to form silicon dioxide; and f. etch the silicon dioxide to form the cavity and diaphragm.

Abstract translation: 一种形成装置的方法，包括在具有上表面的硅衬底上的力换能器，所述硅衬底包括n型或p型中的一种的掺杂剂，所述力传感器包括具有间隔开的侧壁的空腔和隔膜 支撑在空腔中，隔膜在空腔的侧壁之间延伸，包括以下步骤：a。 在衬底中注入n型或p型之一的掺杂剂层; b。 在衬底的上表面上沉积外延层，所述外延层包括n型或p型中另一种的掺杂剂; C。 通过外延层注入间隔的沉降片并与n型或p型之一的掺杂剂层电连接，每个沉降片包括n型或p型之一的掺杂剂， 类型; d。 阳极氧化基板以形成沉降片和层的多孔硅; e。 氧化多孔硅以形成二氧化硅; 和f。 蚀刻二氧化硅以形成空腔和隔膜。

公开(公告)号：US11932531B2

公开(公告)日：2024-03-19

申请号：US17694083

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Jung Chen

IPC: B81B3/00 ,  B81C1/00 ,  G02B7/02 ,  H04N23/54 ,  H04N23/68

CPC classification number: B81B3/0072 ,  B81C1/00666 ,  H04N23/54 ,  H04N23/687 ,  B81B2203/0118 ,  B81B2203/019 ,  B81B2203/0307 ,  B81C2201/0105 ,  B81C2201/0178 ,  G02B7/021

Abstract: The present disclosure relates to an integrated chip structure including a MEMS actuator. The MEMS actuator includes an anchor having a first plurality of branches extending outward from a central region of the anchor. The first plurality of branches respectively include a first plurality of fingers. A proof mass surrounds the anchor and includes a second plurality of branches extending inward from an interior sidewall of the proof mass. The second plurality of branches respectively include a second plurality of fingers interleaved with the first plurality of fingers as viewed in a top-view. One or more curved cantilevers are coupled between the proof mass and a frame wrapping around the proof mass. The one or more curved cantilevers have curved outer surfaces having one or more inflection points as viewed in the top-view.

公开(公告)号：US20230219806A1

公开(公告)日：2023-07-13

申请号：US17694083

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Jung Chen

IPC: B81B3/00 ,  B81C1/00 ,  H04N5/225 ,  H04N5/232

CPC classification number: B81B3/0072 ,  B81C1/00666 ,  H04N5/2253 ,  H04N5/23287 ,  B81B2203/0118 ,  B81B2203/019 ,  B81B2203/0307 ,  B81C2201/0105 ,  B81C2201/0178 ,  G02B7/021

Abstract: The present disclosure relates integrated chip structure including a MEMS actuator. The MEMS actuator includes an anchor having a first plurality of branches extending outward from a central region of the anchor. The first plurality of branches respectively include a first plurality of fingers. A proof mass surrounds the anchor and includes a second plurality of branches extending inward from an interior sidewall of the proof mass. The second plurality of branches respectively include a second plurality of fingers interleaved with the first plurality of fingers as viewed in a top-view. One or more curved cantilevers are coupled between the proof mass and a frame wrapping around the proof mass. The one or more curved cantilevers have curved outer surfaces having one or more inflection points as viewed in the top-view.

公开(公告)号：US11673798B2

公开(公告)日：2023-06-13

申请号：US17084389

申请日：2020-10-29

Applicant: International Business Machines Corporation ,  THE UNIVERSITY OF BASEL

Inventor： Gabriel Fernando Puebla Hellmann ,  Diego Monserrat Lopez ,  Ute Drechsler ,  Marcel Mayor ,  Emanuel Marc Löertscher

IPC: B81C1/00 ,  B81B1/00 ,  B01L3/00

CPC classification number: B81C1/00119 ,  B01L3/502707 ,  B01L3/502715 ,  B81B1/002 ,  B01L2200/12 ,  B01L2300/12 ,  B01L2300/168 ,  B81B2201/058 ,  B81B2203/0353 ,  B81B2203/04 ,  B81C2201/0132 ,  B81C2201/0159 ,  B81C2201/0178

Abstract: A device includes a first layer of an electrically insulating material and a second layer of a non-electrically insulating material (e.g., semiconductor or electrically conductive) extending on the first layer. The second layer is structured so as to define opposite, lateral walls of a microchannel, a bottom wall of which is defined by an exposed surface of the first layer. The second layer is further structured to form one or more electrical insulation barriers; each barrier includes a line of through holes, each surrounded by an oxidized region of the material of the second layer. The through holes alternate with oxidized portions of the oxidized region along the line. Each barrier extends, as a whole, laterally across the second layer up to one of the lateral walls and delimits two sections of the second layer on each side of the barrier and on a same side of the microchannel.

公开(公告)号：US11667524B2

公开(公告)日：2023-06-06

申请号：US17130335

申请日：2020-12-22

Applicant: HYUNDAI KEFICO CORPORATION

Inventor： Jun Hwan Choi ,  Chi Yeon Kim

IPC: B81C1/00 ,  G01L19/06

CPC classification number: B81C1/00357 ,  B81C2201/0133 ,  B81C2201/0176 ,  B81C2201/0178 ,  B81C2201/0195 ,  G01L19/0654

Abstract: Disclose is a method for fabricating a semiconductor device. The method includes: forming a groove such as by etching one side surface of a first substrate; attaching a second substrate including a silicon layer on the etched surface of the first substrate formed with the hollow groove; etching the second substrate so as to leave substantially only the silicon layer; forming a thin film structure on the surface of silicon layers of the second substrate; and separating the second substrate formed with the thin film structure from the first substrate. For example, the groove structure may be formed in the lower portion of the device in the process of fabricating the semiconductor device to facilitate the final device separation.

公开(公告)号：US20170166438A1

公开(公告)日：2017-06-15

申请号：US14969329

申请日：2015-12-15

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0056 ,  B81B2201/012 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/0015 ,  B81C1/00619 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0178 ,  B81C2203/0109 ,  B81C2203/0136 ,  H01H59/0009 ,  H01H2001/0078

Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

公开(公告)号：US08415220B2

公开(公告)日：2013-04-09

申请号：US12709981

申请日：2010-02-22

Applicant: Tymon Barwicz

Inventor： Tymon Barwicz

IPC: H01L21/336

CPC classification number: H01L29/0665 ,  B81B2203/0109 ,  B81C1/00833 ,  B81C2201/0178 ,  B81C2201/053 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

Abstract: Techniques for preventing bending/buckling of suspended micro/nanostructures during oxidation are provided. In one aspect, a method for oxidizing a structure is provided. The method includes providing the structure having at least one suspended element selected from the group consisting of: a microstructure, a nanostructure and a combination thereof; surrounding the at least one suspended element in a cladding material; and oxidizing the at least one suspended element through the cladding material, wherein the cladding material physically constrains and thereby prevents distortion of the at least one suspended element during the oxidation.

Abstract translation: 提供了用于在氧化期间防止悬浮的微/纳米结构的弯曲/屈曲的技术。 一方面，提供一种氧化结构的方法。 该方法包括提供具有至少一个悬浮元素的结构，所述悬浮元素选自：微结构，纳米结构及其组合; 围绕包层材料中的至少一个悬挂元件; 以及通过所述包层材料氧化所述至少一个悬浮元件，其中所述包层材料物理地约束并由此防止所述至少一个悬浮元件在氧化期间的变形。

公开(公告)号：US20120021550A1

公开(公告)日：2012-01-26

申请号：US13176371

申请日：2011-07-05

Applicant: CHRISTEL DIEPPEDALE ,  STEPHAN BOREL ,  BRUNO REIG ,  HENRI SIBUET

Inventor： CHRISTEL DIEPPEDALE ,  STEPHAN BOREL ,  BRUNO REIG ,  HENRI SIBUET

IPC: H01L21/02

CPC classification number: B81C1/00158 ,  B81B2201/018 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2203/0361 ,  B81C1/00492 ,  B81C2201/0178 ,  H01H1/0036

Abstract: The fabrication of a semiconductor fixed structure defining a volume, for example of a MEMS micro electro-mechanical system includes, determining thicknesses beforehand depending on the functional distances associated with elements. At least one element is formed on a substrate by thermal oxidation of the substrate so as to form an oxide layer followed by selective etching of the oxide layer so as to define the volume in an etched portion by baring the underlying substrate so as to define the element in an unetched portion, and later oxidation of the substrate so as to form an oxide layer, in order to obtain the elements at the functional distances.

Abstract translation: 限定体积的半导体固定结构（例如MEMS微机电系统）的制造包括：根据与元件相关联的功能距离预先确定厚度。 通过衬底的热氧化在衬底上形成至少一个元件，以便形成氧化物层，然后选择性地蚀刻氧化物层，以便通过掩埋下面的衬底限定蚀刻部分中的体积，从而限定 元素在未蚀刻部分中，并且随后氧化基底以形成氧化物层，以便在功能距离处获得元件。