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    SURFACE ROUGHENING TO REDUCE ADHESION IN AN INTEGRATED MEMS DEVICE
    41.
    发明申请
    SURFACE ROUGHENING TO REDUCE ADHESION IN AN INTEGRATED MEMS DEVICE 审中-公开
    表面粗糙化以减少集成MEMS器件中的粘合

    公开(公告)号：US20140264655A1

    公开(公告)日：2014-09-18

    申请号：US14061152

    申请日：2013-10-23

    Applicant: InvenSense, Inc.

    Inventor： Kirt Reed WILLIAMS ,  Kegang HUANG ,  Wencheng XU ,  Jongwoo SHIN ,  Martin LIM

    IPC: B81B3/00 ,  B81C1/00

    CPC classification number: B81B3/001 ,  B81C2201/115

    Abstract: In an integrated MEMS device, moving silicon parts with smooth surfaces can stick together if they come into contact. By roughening at least one smooth surface, the effective area of contact, and therefore surface adhesion energy, is reduced and hence the sticking force is reduced. The roughening of a surface can be provided by etching the smooth surfaces in gas, plasma, or liquid with locally non-uniform etch rate. Various etch chemistries and conditions lead to various surface roughness.

    Abstract translation: 在集成的MEMS器件中，移动具有光滑表面的硅部件如果接触则可以粘在一起。 通过使至少一个光滑表面粗糙化，有效的接触面积以及因此的表面附着能减少，因此粘附力降低。 可以通过以局部不均匀蚀刻速率蚀刻气体，等离子体或液体中的光滑表面来提供表面的粗糙化。 各种蚀刻化学和条件导致各种表面粗糙度。

    Surface roughening process
    42.
    发明授权
    Surface roughening process 有权
    表面粗糙化处理

    公开(公告)号：US08268703B2

    公开(公告)日：2012-09-18

    申请号：US11827709

    申请日：2007-07-13

    Applicant: Bernard Aspar ,  Chrystelle Lagahe Blanchard ,  Nicolas Sousbie

    Inventor： Bernard Aspar ,  Chrystelle Lagahe Blanchard ,  Nicolas Sousbie

    IPC: H01L21/30

    CPC classification number: B81C1/00952 ,  B81B3/001 ,  B81C2201/115

    Abstract: A process of forming a rough interface in a semiconductor substrate. The process includes the steps of depositing a material on a surface of the substrate, forming a zone of irregularities in the material, and forming a rough interface in the semiconductor substrate by a thermal oxidation of the material and a part of the substrate. Additionally, the surface of the oxidized material may be prepared and the surface may be assembled with a second substrate.

    Abstract translation: 在半导体衬底中形成粗糙界面的工艺。 该方法包括以下步骤：在衬底的表面上沉积材料，在材料中形成不规则区域，并通过材料和衬底的一部分的热氧化在半导体衬底中形成粗糙界面。 此外，可以制备氧化材料的表面，并且表面可以与第二衬底组装。

    MICROMECHANICAL TUNABLE FABRY-PEROT INTERFEROMETER, AN INTERMEDIATE PRODUCT, AND A METHOD FOR PRODUCING THE SAME
    43.
    发明申请
    MICROMECHANICAL TUNABLE FABRY-PEROT INTERFEROMETER, AN INTERMEDIATE PRODUCT, AND A METHOD FOR PRODUCING THE SAME 有权
    微生物耐压织物干燥仪，中间产品及其生产方法

    公开(公告)号：US20120050751A1

    公开(公告)日：2012-03-01

    申请号：US13319337

    申请日：2010-05-28

    Applicant: Martti Blomberg

    Inventor： Martti Blomberg

    IPC: G01B9/02 ,  H01L21/02

    CPC classification number: G02B26/001 ,  B81B3/0013 ,  B81B2201/042 ,  B81C2201/115 ,  G01J3/26

    Abstract: The invention relates to controllable Fabry-Perot interferometers which are produced with micromechanical (MEMS) technology. Producing prior art interferometers includes a risk of deterioration of mirrors during the etching of the sacrificial layer (123). According to the solution according to the invention at least one layer (103, 105, 114, 116) of the mirrors is made of silicon-rich silicon nitride. In the inventive Fabry-Perot interferometer it is possible to avoid or reduce using silicon oxide in the mirror layers whereby the risk of deterioration of the mirrors is reduced. It is also possible to use mirror surfaces with higher roughness, whereby the risk of the mirrors sticking to each other is reduced.

    Abstract translation: 本发明涉及用微机械（MEMS）技术制造的可控法布里 - 珀罗干涉仪。 生产现有技术的干涉仪包括在蚀刻牺牲层（123）期间反射镜劣化的风险。 根据本发明的解决方案，反射镜的至少一层（103,105,114,116）由富硅的氮化硅制成。 在本发明的法布里 - 珀罗干涉仪中，可以避免或减少使用反射镜层中的氧化硅，从而降低反射镜劣化的风险。 还可以使用具有较高粗糙度的镜面，从而降低了彼此粘附的镜子的风险。

    Micromechanical component and manufacturing method
    44.
    发明授权
    Micromechanical component and manufacturing method 有权
    微机械部件及制造方法

    公开(公告)号：US07919346B2

    公开(公告)日：2011-04-05

    申请号：US12090566

    申请日：2006-11-29

    Applicant: Arnd Kaelberer ,  Jens Frey

    Inventor： Arnd Kaelberer ,  Jens Frey

    IPC: H01L21/00

    CPC classification number: B81C1/00984 ,  B81B3/001 ,  B81C2201/115 ,  Y10T428/24355

    Abstract: A micromechanical component has a substrate, a first intermediate layer which is situated thereupon, and a first layer which is situated thereupon and is structured down to the first intermediate layer. A second intermediate layer is situated above the first layer. A second layer is situated on the former, at least one movable micromechanical structure being structured into the second layer. The second intermediate layer is removed in a sacrificial zone beneath the movable micromechanical structure and the first intermediate layer is partially removed in zones beneath the first layer. The movable micromechanical structure is provided with at least one stop surface on a bottom face, this stop surface being contactable with a zone of the first layer which is supported by the first intermediate layer by deflection of the movable micromechanical structure. A method for producing such a micromechanical component is also described.

    Abstract translation: 微机械部件具有衬底，位于其上的第一中间层和位于其上并且被构造成第一中间层的第一层。 第二中间层位于第一层上方。 第二层位于前者上，至少一个可移动微机械结构被构造成第二层。 第二中间层在可移动微机械结构下面的牺牲区域中被去除，并且第一中间层在第一层下面的区域中被部分地去除。 可移动微机械结构在底面上设置有至少一个止动表面，该止动表面可通过可移动微机械结构的偏转而与第一层的区域接触，该区域由第一中间层支撑。 还描述了一种用于制造这种微机械部件的方法。

    Process of forming and controlling rough interfaces
    45.
    发明申请
    Process of forming and controlling rough interfaces 有权
    形成和控制粗糙界面的过程

    公开(公告)号：US20080176382A1

    公开(公告)日：2008-07-24

    申请号：US11827715

    申请日：2007-07-13

    Applicant: Bernard Aspar ,  Chrystelle Lagahe Blanchard ,  Nicolas Sousbie

    Inventor： Bernard Aspar ,  Chrystelle Lagahe Blanchard ,  Nicolas Sousbie

    IPC: H01L21/30

    CPC classification number: B81B3/001 ,  B81C1/00952 ,  B81C2201/115

    Abstract: The invention provides a method for forming a semiconductor component with a rough buried interface. The method includes providing a first semiconductor substrate having a first surface of roughness R1. The method further includes thermally oxidizing the first surface of the first semiconductor substrate to form an oxide layer defining an external oxide surface on the first semiconductor substrate and a buried oxide-semiconductor interface below the oxide surface, so that the buried oxide surface has a roughness R2 that is less than R1. The method also includes assembling the oxide surface of the first semiconductor substrate with a second substrate. The invention also provides a component formed according to the method of the invention.

    Abstract translation: 本发明提供一种用于形成具有粗糙掩埋界面的半导体部件的方法。 该方法包括提供具有粗糙度R 1的第一表面的第一半导体衬底。 该方法还包括热氧化第一半导体衬底的第一表面以形成限定第一半导体衬底上的外部氧化物表面的氧化物层和氧化物表面下方的掩埋氧化物半导体界面，使得掩埋氧化物表面具有粗糙度 R 2小于R 1。 该方法还包括用第二衬底组装第一半导体衬底的氧化物表面。 本发明还提供了根据本发明的方法形成的部件。

    Method for separating a useful layer and component obtained by said method
    46.
    发明申请
    Method for separating a useful layer and component obtained by said method 失效
    用于分离由所述方法获得的有用层和组分的方法

    公开(公告)号：US20060144816A1

    公开(公告)日：2006-07-06

    申请号：US10562931

    申请日：2004-07-01

    Applicant: Hubert Grange ,  Bernard Diem ,  Sylvie Viollet Bosson ,  Michel Borel

    Inventor： Hubert Grange ,  Bernard Diem ,  Sylvie Viollet Bosson ,  Michel Borel

    IPC: C03C15/00

    CPC classification number: B81B3/001 ,  B81C2201/115

    Abstract: A useful layer (1) is initially attached by a sacrificial layer (2) to a layer (3) forming a substrate. Before etching of the sacrificial layer (2), at least a part of the surface (4, 5) of at least one of the layers in contact with the sacrificial layer (2) is doped. After etching of the sacrificial layer (2), the surface (4, 5) is superficially etched so as to increase the roughness of its doped part. After doping, a mask (9) is deposited on a part of the useful layer (1) so as to delineate a doped zone and a non-doped zone of the surface (4, 5), one of the zones forming a stop after the superficial etching phase.

    Abstract translation: 有用层（1）最初由牺牲层（2）附着到形成衬底的层（3）上。 在蚀刻牺牲层（2）之前，掺杂与牺牲层（2）接触的至少一层的表面（4,5）的至少一部分。 在蚀刻牺牲层（2）之后，表面（4,5）被表面蚀刻以增加其掺杂部分的粗糙度。 在掺杂之后，在有用层（1）的一部分上沉积掩模（9），以便描绘表面（4,5）的掺杂区和非掺杂区，其中一个区在 表面蚀刻阶段。

    METHOD FOR FABRICATING NANO-SCALE PATTERNED SURFACES
    50.
    发明公开
    METHOD FOR FABRICATING NANO-SCALE PATTERNED SURFACES 审中-公开
    用于生产纳米结构表面

    公开(公告)号：EP2252545A2

    公开(公告)日：2010-11-24

    申请号：EP09719665.3

    申请日：2009-03-10

    Applicant: Yeda Research And Development Company Ltd.

    Inventor： NAAMAN, Ron ,  GOLAN, Ben ,  FRADKIN, Zeev ,  WINKLEMAN, Adam ,  ORON, Dan

    IPC: B81C1/00

    CPC classification number: B81C1/00206 ,  B81C1/00031 ,  B81C2201/0132 ,  B81C2201/115 ,  G03F7/40

    Abstract: A method for fabrication of substrate having a nano-scale surface roughness is presented. The method comprises: patterning a surface of a substrate to create an array of spaced-apart regions of a light sensitive material; applying a controllable etching to the patterned surface, said controllable etching being of a predetermined duration selected so as to form a pattern with nano-scale features; and removing the light sensitive material, thereby creating a structure with the nano-scale surface roughness. Silanizing such nano-scale roughness surface with hydrophobic molecules results in the creation of super- hydrophobic properties characterized by both a large contact angle and a large tilting angle. Also, deposition of a photo-active material on the nano-scale roughness surface results in a photocathode with enhanced photoemission yield. This method also provides for fabrication of a photocathode insensitive to polarization of incident light.

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