公开(公告)号：US12086597B2

公开(公告)日：2024-09-10

申请号：US17361250

申请日：2021-06-28

Applicant: Silicon Laboratories Inc.

Inventor： Matthew Brandon Gately ,  Eric Jonathan Deal ,  Mark Willard Johnson

IPC: G06F9/32 ,  G06F9/345

CPC classification number: G06F9/325 ,  G06F9/3455

Abstract: An apparatus includes an array processor to process at least one array. The apparatus further includes a memory coupled to the array processor. The at least one array is stored in memory with programmable per-dimension size and stride values.

公开(公告)号：US20240295891A1

公开(公告)日：2024-09-05

申请号：US18177842

申请日：2023-03-03

Applicant: Silicon Laboratories Inc.

Inventor： Sagar Kumar

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: A voltage regulator includes a first circuit to generate a difference signal based on an input reference voltage, a regulated output voltage, and a signal on a feedback node. The voltage regulator includes a second circuit to provide the regulated output voltage on the output node based on the difference signal. The second circuit includes a first transistor coupled to receive the difference signal, a first feedback circuit to provide a first feedback signal to the feedback node, and a second feedback circuit to provide a second feedback signal to the feedback node. An open loop frequency response of the voltage regulator has a first pole and a second pole and the first feedback signal may adjust the frequency of the second pole based on a load current. The second feedback signal may adjust loop gain based on the load current.

公开(公告)号：US20240292331A1

公开(公告)日：2024-08-29

申请号：US18175623

申请日：2023-02-28

Applicant: Silicon Laboratories Inc.

Inventor： Yi Shen Yeh ,  Yan Zhou ,  Marc Leroux

IPC: H04W52/02 ,  H04L27/02

CPC classification number: H04W52/0229 ,  H04L27/02

Abstract: In an embodiment, an apparatus includes a baseband processor comprising: a packet generation circuit to generate a wake-up packet comprising information to cause a first receiver to trigger a wake-up of a second receiver; an encoder to encode the wake-up packet with Manchester encoding to output Manchester encoded on-off keying (MOOK) data; and a modulator coupled to the encoder to receive random data and modulate the random data. This modulated random data may be amplitude modulated with the MOOK data to realize a radio frequency (RF) signal comprising the MOOK data that is to be transmitted to one or more receivers.

公开(公告)号：US20240276537A1

公开(公告)日：2024-08-15

申请号：US18169572

申请日：2023-02-15

Applicant: Silicon Laboratories Inc.

Inventor： Jitesh Rachamadugu ,  Suresh Babu Sykam

IPC: H04W72/566

CPC classification number: H04W72/569 ,  H04W80/02

Abstract: A technique for reducing latency of high priority asynchronous traffic in the presence of isochronous traffic of a Bluetooth™ Low Energy communications system includes communicating an Asynchronous Connection Link (ACL) payload using a Connected Isochronous Stream (CIS) event. A bit in a header of a host-controller interface packet indicates to the controller that an ACL packet is a high priority ACL packet. The controller replaces the payload of a CIS event with the payload of the high priority ACL packet and the controller encodes a bit in a header of the CIS packet to signal to the receiving device that a corresponding CIS event contains an ACL payload. The controller transmits the CIS packet in the corresponding CIS event and the receiving device applies ACL handling of the CIS event in response to decoding the bit in the header of the CIS packet.

公开(公告)号：US20240267005A1

公开(公告)日：2024-08-08

申请号：US18639872

申请日：2024-04-18

Applicant: Silicon Laboratories Inc.

Inventor： Rangakrishnan Srinivasan ,  Mustafa H. Koroglu ,  Zhongda Wang ,  Francesco Barale ,  Abdulkerim L. Coban ,  John M. Khoury ,  Sriharsha Vasadi ,  Michael S. Johnson ,  Vitor Pereira

IPC: H03F1/26 ,  H03B5/04 ,  H03F1/30 ,  H03F3/24 ,  H03K5/00

CPC classification number: H03F1/26 ,  H03B5/04 ,  H03F1/30 ,  H03F3/245 ,  H03K5/00 ,  H03F2200/375 ,  H03K2005/00019

Abstract: A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to amplify the delayed oscillating signal for transmission sufficient to produce interference, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.

公开(公告)号：US12045645B2

公开(公告)日：2024-07-23

申请号：US16945871

申请日：2020-08-02

Applicant: Silicon Laboratories Inc.

Inventor： Subba Reddy Kallam ,  Partha Sarathy Murali ,  Venkat Mattela ,  Venkata Siva Prasad Pulagam

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  H04L49/90 ,  H04L65/60 ,  H04W4/80 ,  H04W12/06 ,  H04W80/02 ,  H04W80/04

CPC classification number: G06F9/4812 ,  G06F9/30101 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/5061 ,  H04L49/90 ,  H04L65/60 ,  H04W4/80 ,  H04W12/06 ,  H04W80/02 ,  H04W80/04

Abstract: A communication processor is operative to adapt the thread allocation to communications processes handled by a multi-thread processor on an instruction by instruction basis. A thread map register controls the allocation of each processor cycle to a particular thread, and the thread map register is reprogrammed as the network process loads for a plurality of communications processors such as WLAN, Bluetooth, Zigbee, or LTE have load requirements which increase or decrease. A thread management process may dynamically allocate processor cycles to each respective process during times of activity for each associated communications process.

公开(公告)号：US12040924B1

公开(公告)日：2024-07-16

申请号：US18172913

申请日：2023-02-22

Applicant: Silicon Laboratories Inc.

Inventor： Hendricus De Ruijter ,  Robert Gorday

IPC: H04L27/22 ,  H03H7/00 ,  H04L27/233

CPC classification number: H04L27/2334 ,  H04L27/2335

Abstract: A cluster correlator may be configured with: a first stage comprising a set of first correlators to correlate samples of an input signal with a first predetermined pattern and output an output sample, the set of first correlators to output a sample cluster corresponding to the output sample of the set of first correlators during a switching cycle of the first stage; a filter coupled to an output of the first stage to receive the sample cluster and to produce a processed output sample based on the sample cluster; and a second stage comprising at least one second correlator to receive a processed output sample from the filter and correlate the processed output sample with a second predetermined pattern, and output one or more correlation outputs during a switching cycle of the second stage.

公开(公告)号：US12039013B2

公开(公告)日：2024-07-16

申请号：US18344129

申请日：2023-06-29

Applicant: Silicon Laboratories Inc.

Inventor： Javier Elenes ,  Antonio Torrini

IPC: G06F18/21 ,  G06F18/20 ,  G06F18/214 ,  G06F18/25 ,  G06N3/088

CPC classification number: G06F18/2193 ,  G06F18/2148 ,  G06F18/251 ,  G06F18/285 ,  G06N3/088

Abstract: In an embodiment, an apparatus includes: a sensor to sense real world information; a digitizer coupled to the sensor to digitize the real world information into digitized information; a signal processor coupled to the digitizer to process the digitized information into an image; a discriminator coupled to the signal processor to determine, based at least in part on the image, whether the real world information comprises an anomaly, where the discriminator is trained via a generative adversarial network; and a controller coupled to the discriminator.

公开(公告)号：US12028024B2

公开(公告)日：2024-07-02

申请号：US16705868

申请日：2019-12-06

Applicant: Silicon Laboratories Inc.

Inventor： Rangakrishnan Srinivasan ,  Mustafa H. Koroglu ,  Zhongda Wang ,  Francesco Barale ,  Abdulkerim L Coban ,  John M. Khoury ,  Sriharsha Vasadi ,  Michael S. Johnson ,  Vitor Pereira

IPC: H03F1/26 ,  H03B5/04 ,  H03F1/30 ,  H03F3/24 ,  H03K5/00

CPC classification number: H03F1/26 ,  H03B5/04 ,  H03F1/30 ,  H03F3/245 ,  H03K5/00 ,  H03F2200/375 ,  H03K2005/00019

Abstract: A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to use the delayed oscillating signal for transmitting a signal, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.

公开(公告)号：US12019124B2

公开(公告)日：2024-06-25

申请号：US17215723

申请日：2021-03-29

Applicant: Silicon Laboratories Inc.

Inventor： Jeffrey L. Sonntag ,  Timothy J. Dupuis ,  Jinwen Xiao

IPC: G01R31/387 ,  G01R31/3832 ,  G01R31/385

CPC classification number: G01R31/387 ,  G01R31/3833 ,  G01R31/385

Abstract: A calibration current load is selectively coupled to an output of a pulse frequency modulated (PFM) DC-DC converter during a calibration operation to increase charge supplied from a battery supplying an input voltage to the converter. A voltage across a sense resistor in series with the battery is integrated during a measurement interval while the calibration current load is coupled to the output. A charge drawn per pulse from the battery is determined based on the sense resistor, the integrated voltage and the number of pulses during the measurement interval. Alternatively, a first PFM frequency is determined with a first calibration current load coupled to the converter output. A second PFM frequency is determined with a second calibration current load. The charge drawn per pulse from the battery is determined based on the first and second PFM frequencies and the first and second calibration current loads.