Access of two synchronous busses with asynchronous clocks to a synchronous single port ram
    51.
    发明公开
    Access of two synchronous busses with asynchronous clocks to a synchronous single port ram 有权
    Zugang von zwei同步Bussen mit asynchronem Takt zu einem同步Einport-RAM

    公开(公告)号:EP1489521A1

    公开(公告)日:2004-12-22

    申请号:EP03447153.2

    申请日:2003-06-16

    Inventor: Levy, David

    CPC classification number: G11C7/1093 G11C7/1006 G11C7/1078

    Abstract: The present invention is related to a method to control the access of two synchronous busses with asynchronous clocks with unknown relative speed to a single port Random Access Memory (RAM), comprising the steps of :

    a) Providing a synchronisation system comprising two busses and a control flip-flop being clocked to the clock of one of said busses,
    b) Providing a signal to said control flip-flop requesting a change of the clock of said RAM, resulting in a control flip-flop output signal,
    c) Applying said control flip-flop output signal to an inverter circuit yielding a signal INV_out and to a circuit to synchronise said output signal to the clock of the bus not in control of said control flip-flop, yielding a signal CL_SW,
    d) Applying the signal INV_out and the signal CL_SW each to a circuit to synchronise to the clock of the other bus yielding signals INV_out_SW and CL_SW_SW, respectively,
    e) Applying the signal INV_OUT and the signal CL_SW_SW to a first combinatorial block outputting a signal en1_comb and applying the signal CL_SW and the signal INV_OUT_SW to a second combinatorial block outputting a signal en2_comb,
    f) Applying the signal en1_comb and the signal en2_comb each to a falling edge sampling flip-flop, yielding signals en1 and en2, respectively,
    g) Applying the signal en1 and the clock of the bus in control of said control flip-flop to an AND gate and the signal en2 and the clock of the other bus to an AND gate, and the outputs of said AND gates to an OR gate,
    h) Using the output signal of said OR gate as the clock signal of said RAM
    i) Applying the signals en1 and en2 to a combinatorial block that outputs the select signal selecting between said busses to the control and data multiplexers used for communication with said single port RAM.

    Abstract translation: 本发明涉及一种用于控制具有与单端口随机存取存储器(RAM)的未知相对速度的异步时钟的两个同步总线的访问的方法,包括以下步骤:a)提供包括两个总线的同步系统和 控制触发器被计时到所述总线中的一个的时钟,b)向所述控制触发器提供请求改变所述RAM的时钟的信号,从而产生控制触发器输出信号,c)应用所述 控制触发器输出信号到逆变器电路,产生一个信号INV_out和一个电路,使所述输出信号与不在所述控制触发器的控制下的总线的时钟同步,产生信号CL_SW,d)应用信号INV_out 和信号CL_SW分别与电路同步的另一总线的时钟,分别产生信号INV_out_SW和CL_SW_SW,e)将信号INV_OUT和信号CL_SW_SW应用于第一组合块输出 信号en1_comb,并将信号CL_SW和信号INV_OUT_SW施加到输出信号en2_comb的第二组合块,f)分别将信号en1_comb和信号en2_comb应用于下降沿采样触发器,分别产生信号en1和en2, g)在所述控制触发器的控制中将信号en1和时钟施加到与门,并将信号en2和另一总线的时钟作为与门,将所述与门的输出连接到OR 门)h)使用所述OR门的输出信号作为所述RAM的时钟信号i)将信号en1和en2施加到组合块,该组合块将在所述总线之间选择的选择信号输出到用于与 表示单端口RAM。

    Time domain equalization using frequency domain operations
    52.
    发明公开
    Time domain equalization using frequency domain operations 审中-公开
    Zeitbereichsentzerrung mittels Operationen im Frequenzbereich

    公开(公告)号:EP1434401A1

    公开(公告)日:2004-06-30

    申请号:EP02447271.4

    申请日:2002-12-24

    CPC classification number: H04L25/03159 H04L25/03012 H04L27/2647

    Abstract: An equalizer for a multi carrier transmission system, converts a transmitted multi carrier signal into sampled frequency domain signals, and suppresses time domain delay dispersion, on the sampled frequency domain signals. It exploits circulant decomposition of a Toeplitz matrix to enable the computationally heavy evaluation of a matrix multiplied by a vector, to be avoided. Increased precision arises from the frequency domain processing being equivalent to a longer time domain FIR filter than is normally practical. The amount of compensation for different carriers can be adjusted, which can lead to increased precision.

    Abstract translation: 一种用于多载波传输系统的均衡器,将所发送的多载波信号转换为采样的频域信号,并对采样的频域信号抑制时域延迟色散。 它利用Toeplitz矩阵的循环分解,使得能够计算重估计矩阵乘以一个向量,以避免。 与通常实际相比,频域处理相当于更长时间的FIR滤波器产生的精度提高。 可以调整不同载体的补偿量,从而提高精度。

    Inter-carrier interference reduction for multi-carrier signals
    54.
    发明公开
    Inter-carrier interference reduction for multi-carrier signals 有权
    Zwischenträger-InterferenzreduzierungfürMehrträgersignale

    公开(公告)号:EP2146470A1

    公开(公告)日:2010-01-20

    申请号:EP08160469.6

    申请日:2008-07-15

    Inventor: Wernaers, Yves

    CPC classification number: H04L27/2647 H04L25/03133

    Abstract: In mobile, wireless communication systems the channel between the transmitter and receiver varies during a transmission. This is often referred to as fading, of which different kinds exist. Each resulting in different impairments with specific properties.
    A low complexity scheme is described to reduce the noise created by inter-carrier interference or ICI. The method makes use of the guard interval and first order Taylor approximation of slow varying channel. It is not restricted to wireless communication and can be used in any environment with varying channels.

    Abstract translation: 在移动,无线通信系统中,发射机和接收机之间的信道在传输过程中发生变化。 这通常被称为衰落,其中存在不同的种类。 每个产生具有特定性质的不同损伤。 描述低复杂度方案以减少由载波间干扰或ICI产生的噪声。 该方法利用缓慢变化信道的保护间隔和一阶泰勒近似。 它不限于无线通信,并且可以在具有不同信道的任何环境中使用。

    A method and system for optimizing power consumption and reducing MIPS requirements for wireless communication
    56.
    发明公开
    A method and system for optimizing power consumption and reducing MIPS requirements for wireless communication 审中-公开
    方法和系统,用于优化能量消耗和减少的用于无线通信的MIPS需求

    公开(公告)号:EP1976226A1

    公开(公告)日:2008-10-01

    申请号:EP08153587.4

    申请日:2008-03-28

    CPC classification number: H04L69/32 H04L69/12 H04W52/0258 H04W76/10 Y02D70/144

    Abstract: The present invention discloses a system and a methodology for enhancing performance during wireless communications by reducing system latency, MIPS requirements and power consumption. The present invention discloses a system and method of wireless data communication in which part of upper layer stack processing is performed on a controller to relieve a host processor of some data intensive operations. After the initial connection establishment phase in which the controller retrieves certain information required for data transmission and stores the same locally, the data source provides data directly to the controller without routing the data through the host. The host is relieved of the data processing that needs to be done while the data is being transferred. Hence, the overall latency of the system is improved because of the optimal routing of data traffic. The host can even go to lower power modes while the controller is performing the data operations on behalf of the upper layer stack thereby saving power consumption of the overall system.

    Abstract translation: 本发明盘松系统以及用于通过减少系统等待时间,MIPS需求和功率消耗提高在无线通信期间的性能的方法。 本发明盘松动的系统和在上层堆栈处理的哪一部分的无线数据通信的方法中执行的控制器上,以减轻someData密集型操作的主处理器。 初始连接建立阶段,其中控制器在本地检索数据传输所需的某些信息,并存储相同的后,数据源直接提供数据到控制器,而不通过主机路由该数据。 主机被解除了数据处理的根本需求,而数据被传输到完成。 因此,系统的总体等待时间由于数据通信的最优路由,改进。 主机甚至可以到低功率模式的同时,所述控制器被代表上层堆栈从而节省了整个系统的功耗的执行数据操作。

    Radio coexistence mechanism for variable data rate radio links
    57.
    发明公开
    Radio coexistence mechanism for variable data rate radio links 有权
    Funkovbindungen mit Variabler Datenrate的Funkkoexistenz机制

    公开(公告)号:EP1959612A1

    公开(公告)日:2008-08-20

    申请号:EP07003400.4

    申请日:2007-02-19

    Abstract: A device has a radio transmitter (10) for a first radio link such as a Bluetooth link, having a coexistence controller (60) arranged to communicate with a co located other radio transmitter (30) for another radio link, to enable both radio links to use potentially conflicting transmission frequencies. A link monitor (50) monitors the first radio link, according to an output from the coexistence controller. By making the link monitor dependent on the coexistence controller, it can distinguish between transmission losses caused by the coexistence interface, and those caused by other effects, to reduce the risk of a data rate controller unnecessarily reducing a transmission rate if transmission losses caused by the coexistence control are misinterpreted as a drop in link quality.

    Abstract translation: 一种设备具有用于诸如蓝牙链路的第一无线电链路的无线电发射机(10),具有被布置为与另一个无线电链路的位于其他无线电发射机(30)的位置进行通信的共存控制器(60),以使无线电链路 使用潜在的冲突传输频率。 链路监视器(50)根据来自共存控制器的输出监视第一无线电链路。 通过使链路监视器取决于共存控制器,它可以区分由共存接口引起的传输损耗和由其他影响引起的传输损耗,以降低数据速率控制器的风险,不必要地降低传输速率,如果传输损耗由 共存控制被误解为链路质量下降。

    Receiver with a two-stages frequency offset compensation for an M-state phase modulated signal

    公开(公告)号:EP1753194A1

    公开(公告)日:2007-02-14

    申请号:EP05447185.9

    申请日:2005-08-12

    CPC classification number: H04L27/22 H04L2027/0065 H04L2027/0095

    Abstract: Method and apparatus for a wireless receiver are described which derive at least a first stream of first digitized samples (30) from a received analog signal at a first sampling rate and identify a first frequency offset of the first stream based on a plurality of parallel correlations (40) using complex reference signals (38) which differ from each other by phase offsets. A second frequency offset is identified (48) based on tracking a demodulation accuracy for each symbol which is demodulated from the first stream of digitized samples. These frequency offsets can be used to rotate decision areas in the demodulator.
    The methods and apparatus may be used in a Bluetooth receiver.

    Abstract translation: 描述了用于无线接收机的方法和装置,其以第一采样率从接收到的模拟信号中导出至少第一数字化样本的第一流(30),并且基于多个并行相关性来识别第一流的第一频率偏移 (40)使用由相位偏移彼此不同的复参考信号(38)。 基于从第一数字化样本流解调的每个符号跟踪解调精度,识别第二频率偏移(48)。 这些频率偏移可用于旋转解调器中的判定区域。 方法和装置可以用在蓝牙接收机中。

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