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公开(公告)号：KR1020140090281A
公开(公告)日：2014-07-17
申请号：KR1020120143410
申请日：2012-12-11
Applicant: 삼성전자주식회사
CPC classification number: G09G5/363 , G09G2320/103 , G09G2352/00 , G09G2360/08
Abstract: Disclosed is a display controller. The display controller includes at least one first power domain which becomes on/off according to a type of image data, and at least one second power domain which always supplies power regardless of the type of image data.
Abstract translation: 公开了一种显示控制器。 显示控制器包括根据图像数据的类型变成开/关的至少一个第一功率域，以及不管图像数据的类型，总是提供功率的至少一个第二功率域。
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公开(公告)号：KR1020140064053A
公开(公告)日：2014-05-28
申请号：KR1020120130947
申请日：2012-11-19
Applicant: 삼성전자주식회사
IPC: H01L23/538
CPC classification number: H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/4813 , H01L2224/48137 , H01L2224/48145 , H01L2224/48147 , H01L2224/48463 , H01L2224/49175 , H01L2224/73265 , H01L2225/06562 , H01L2924/15311 , H01L2924/181 , H01L2924/19104 , H01L2924/00 , H01L2924/00012
Abstract: Multiple first semiconductor chips having data pads and power pads are mounted on a substrate. An upper wiring layer having multiple redistribution patterns and multiple redistribution pads on an upper-most first semiconductor chip among the first semiconductor chips is formed. A second semiconductor chip adjacent to the data pads is mounted on the upper-most first semiconductor chip. A first passive element electrically connected to the second semiconductor chip is formed on the upper-most first semiconductor chip. First conductive connections are formed between the data pads and the second semiconductor chip. Second conductive connections are formed between the second semiconductor chip and the substrate. The data pads of the first semiconductor chips are electrically connected to the substrate via the first conductive connections, the second semiconductor chip, the redistribution patterns, the redistribution pads and the second conductive connections.
Abstract translation: 具有数据焊盘和电源焊盘的多个第一半导体芯片安装在基板上。 形成在第一半导体芯片中的最上面的第一半导体芯片上具有多个再分配图案和多个再分配焊盘的上部布线层。 与数据焊盘相邻的第二半导体芯片安装在最上面的第一半导体芯片上。 电连接到第二半导体芯片的第一无源元件形成在最上面的第一半导体芯片上。 在数据焊盘和第二半导体芯片之间形成第一导电连接。 在第二半导体芯片和基板之间形成第二导电连接。 第一半导体芯片的数据焊盘经由第一导电连接，第二半导体芯片，再分布图案，再分布焊盘和第二导电连接电连接到基板。
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公开(公告)号：KR1020140022255A
公开(公告)日：2014-02-24
申请号：KR1020120088628
申请日：2012-08-13
Applicant: 삼성전자주식회사
Inventor： 김경만
CPC classification number: H01L23/04 , H01L21/56 , H01L23/3128 , H01L24/73 , H01L25/105 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2924/1461 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H01L2924/00012 , H01L2924/00
Abstract: Disclosed is a semiconductor package of a PoP shape capable of forming a fine pitch. The semiconductor package according to the present invention includes a lower printed circuit board in which one or more lower semiconductor chips are attached on the upper surface; an upper printed circuit board arranged on the lower printed circuit board and in which one or more upper semiconductor chips are attached on the upper surface; a lower mold layer formed on the upper surface of the lower printed circuit board to be arranged between the lower printed circuit board and the upper printed circuit board; a first partial space formed in the lower mold layer; a second partial space formed in the first partial space; a via hole penetrating the lower mold layer; and a solder layer electrically connecting the upper printed circuit board and the lower printed circuit board and penetrating the via hole. A horizontal cross section of the first partial space is changed according to the whole height of the first partial space, and the lowermost horizontal cross section of the second partial space is gradually reduced from the upper surface of the lower mold layer to the inside of the lower mold layer.
Abstract translation: 公开了能够形成细间距的PoP形状的半导体封装。 根据本发明的半导体封装包括下印刷电路板，其中一个或多个下半导体芯片附着在上表面上; 布置在下印刷电路板上的上印刷电路板，其中一个或多个上半导体芯片附着在上表面上; 形成在下印刷电路板的上表面上以形成在下印刷电路板和上印刷电路板之间的下模层; 形成在下模层中的第一部分空间; 形成在所述第一部分空间中的第二部分空间; 穿过下模层的通孔; 以及焊接层，电连接上印刷电路板和下印刷电路板并穿透通孔。 第一部分空间的水平截面根据第一部分空间的整体高度而改变，并且第二部分空间的最低水平截面从下模层的上表面逐渐减小到 下模层。
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公开(公告)号：KR1020140013652A
公开(公告)日：2014-02-05
申请号：KR1020120081600
申请日：2012-07-26
Applicant: 삼성전자주식회사
IPC: G09G3/20
CPC classification number: G09G5/003 , G09G3/20 , G09G2330/021 , G09G2330/022 , G09G2340/0435 , G09G2340/16
Abstract: A system on chip includes a frame buffer, a mode detector, a first and a second display sub system, and an output buffer. The frame buffer supplies internal image data corresponding to input image data by frame. The mode detector generates a mode detecting signal representing an operation mode according to the power consumption based on the input image data. The first display sub system generates first image data and a first control signal based on the internal image data and the mode detecting signal. The second display sub system generates second image data and a second control signal based on the internal image data and the mode detecting signal. The first and the second display sub system are complementarily activated based on the mode detecting signal. The output buffer outputs one among the first and the second image data and one among the first and the second control signal based on the mode detecting signal.
Abstract translation: 片上系统包括帧缓冲器，模式检测器，第一和第二显示子系统以及输出缓冲器。 帧缓冲器逐帧提供对应于输入图像的内部图像数据。 模式检测器基于输入的图像数据生成表示根据功耗的操作模式的模式检测信号。 第一显示子系统基于内部图像数据和模式检测信号生成第一图像数据和第一控制信号。 第二显示子系统基于内部图像数据和模式检测信号生成第二图像数据和第二控制信号。 第一和第二显示子系统基于模式检测信号互补地激活。 输出缓冲器基于模式检测信号在第一和第二图像数据中输出一个，并且在第一和第二控制信号中输出一个。
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公开(公告)号：KR101248907B1
公开(公告)日：2013-03-28
申请号：KR1020080019210
申请日：2008-02-29
Applicant: 삼성전자주식회사
CPC classification number: H04N1/603
Abstract: 화상형성장치 및 그의 색상 테이블 생성 방법과 칼라 문서 출력 방법이 개시된다. 본 발명의 일 실시예에 따른 화상형성장치는, 기설정된 개수의 색상을 사용하는 칼라 문서를 구성하는 색상을 화상형성장치에서 구현 가능한 색상과 매칭하는 색상 매칭부, 및 매칭된 색상을 이용하여 색상 테이블을 생성하는 색상테이블 생성부를 포함한다. 이에 의해, 프린터와 스캐너 간의 특성 차이로 인해 발생하는 칼라 변이를 줄일 수 있다.
화상형성장치, 지도 복사, 인덱스, 색상 테이블, 색상 매칭-
Patent Agency Ranking
公开(公告)号：KR1020120088100A
公开(公告)日：2012-08-08
申请号：KR1020110009203
申请日：2011-01-31
Applicant: 삼성전자주식회사
CPC classification number: G06T15/503 , H04N13/161 , H04N13/305 , H04N13/31 , H04N13/324 , H04N13/337 , H04N13/341 , H04N13/398 , G02B27/22
Abstract: PURPOSE: A display controller and a display system are provided to support a 3D image mode without adding a complicated circuit. CONSTITUTION: A blending coefficient storage unit(130) stores blending coefficients. An image mixing unit(110) receives left eye image data and right eye image data. The image mixing unit performs a blending operation of the left eye image data and the right eye image data using the blending coefficients stored in the blending coefficient storage unit. The image mixing unit generates 3D image data.
Abstract translation: 目的：提供显示控制器和显示系统，以支持3D图像模式，而不会增加复杂的电路。 构成：混合系数存储单元（130）存储混合系数。 图像混合单元（110）接收左眼图像数据和右眼图像数据。 图像混合单元使用存储在混合系数存储单元中的混合系数来执行左眼图像数据和右眼图像数据的混合操作。 图像混合单元生成3D图像数据。
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公开(公告)号：KR1020120016451A
公开(公告)日：2012-02-24
申请号：KR1020100078819
申请日：2010-08-16
Applicant: 삼성전자주식회사
CPC classification number: H04N1/6058
Abstract: PURPOSE: A print control terminal unit and a color correcting method are provided to generate a color conversion table according to a user's taste, thereby generating print data using the generated color conversion table. CONSTITUTION: An input unit(130) selects color reproduction targets, an input ICC profile, and an output ICC profile to be applied to an ICC(International Color Consortium) profile. A color reproduction generating unit(150) generates a color conversion image using the color reproduction targets, the selected input ICC profile, and the selected output ICC profile. A driver unit(160) generates print data using the generated color conversion table. A communications interface unit(110) transmits the generated print data to an image forming device.
Abstract translation: 目的：提供打印控制终端单元和颜色校正方法以根据用户的口味产生颜色转换表，从而使用生成的颜色转换表生成打印数据。 构成：输入单元（130）选择要应用于ICC（国际色彩联盟）配置文件的色彩再现目标，输入ICC配置文件和输出ICC配置文件。 色彩再现产生单元（150）使用颜色再现目标，所选择的输入ICC曲线和所选择的输出ICC曲线生成颜色转换图像。 驱动器单元（160）使用生成的颜色转换表生成打印数据。 通信接口单元（110）将生成的打印数据发送到图像形成装置。
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公开(公告)号：KR1020100121231A
公开(公告)日：2010-11-17
申请号：KR1020090040290
申请日：2009-05-08
Applicant: 삼성전자주식회사
CPC classification number: H01L23/49811 , H01L23/3128 , H01L23/49816 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48195 , H01L2224/48227 , H01L2224/4911 , H01L2224/73265 , H01L2224/92247 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19107 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
Abstract: PURPOSE: A package on package preventing circuit pattern lift defect and a method for fabricating the same are provided to prevent the cleavage defect of a circuit pattern caused by the stress of temperature variation by implementing a role of a buffer layer which absorbs the stress by the temperature variation. CONSTITUTION: A package manufacturing substrate(110) is prepared. A plurality of semiconductor chips(116) is laminated on the substrate. A pad redistribution pattern(118) is formed on the laminated top part of semiconductor chip. A copper post(120) is formed on a connection terminal of the pad redistribution pattern.
Abstract translation: 目的：提供封装封装防止电路图案提升缺陷及其制造方法，以通过实现吸收应力的缓冲层的作用来防止由温度变化的应力引起的电路图案的裂纹缺陷 温度变化。 构成：制备包装制造衬底（110）。 多个半导体芯片（116）层叠在基板上。 在半导体芯片的层叠顶部形成有衬垫再分布图案（118）。 在焊盘再分布图案的连接端子上形成铜柱（120）。
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公开(公告)号：KR1020100104373A
公开(公告)日：2010-09-29
申请号：KR1020090022748
申请日：2009-03-17
Applicant: 삼성전자주식회사
CPC classification number: H01L23/49575 , H01L23/49555 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/525 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48245 , H01L2224/48247 , H01L2224/73265 , H01L2225/06565 , H01L2225/1023 , H01L2225/1041 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: PURPOSE: A stacked semiconductor package apparatus is provided to improve conductivity and prevent a solder joint defect. CONSTITUTION: A stacked semiconductor package apparatus includes a first semiconductor package(100), a second semiconductor package(200), and a signal connection member(10). The first semiconductor package comprises one or more first semiconductor chips and a first encapsulating material to protect the first semiconductor chip. The second semiconductor package includes one or more second semiconductor chips, a lead connected to the second semiconductor chip and a second encapsulating material. The signal connection member passes through the first encapsulating material of the first semiconductor package and connects the first semiconductor chip with the second semiconductor chip.
Abstract translation: 目的：提供一种叠层半导体封装装置，以提高导电性并防止焊点缺陷。 构成：叠层半导体封装装置包括第一半导体封装（100），第二半导体封装（200）和信号连接构件（10）。 第一半导体封装包括一个或多个第一半导体芯片和用于保护第一半导体芯片的第一封装材料。 第二半导体封装包括一个或多个第二半导体芯片，连接到第二半导体芯片的引线和第二封装材料。 信号连接部件穿过第一半导体封装的第一封装材料并将第一半导体芯片与第二半导体芯片连接。
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公开(公告)号：KR1020100099573A
公开(公告)日：2010-09-13
申请号：KR1020090018129
申请日：2009-03-03
Applicant: 삼성전자주식회사
Inventor： 김경만
IPC: H01L23/045 , H01L23/12
CPC classification number: H01L21/76898 , H01L25/0657 , H01L2224/02372 , H01L2224/0401 , H01L2224/05554 , H01L2224/0557 , H01L2224/05572 , H01L2224/13009 , H01L2224/13024 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/01078 , H01L2224/05552
Abstract: PURPOSE: A semiconductor device and a method for manufacturing the same are provided to improve the mechanical junction intensity by forming a dummy through electrode in a cell region or a scribe lane in order to obtain a parallel electric connection. CONSTITUTION: A cell region(105) with a pad(110) and a scribe lane region(106) defining the cell region are prepared in a substrate(107). A through electrode(160) is electrically connected with the pad. A dummy through electrode(170) is electrically connected with the through electrode. A conductive pattern(152) is electrically connected with the through electrode and the dummy through electrode. A passivation layer(140) protects the front side(102) of the substrate.
Abstract translation: 目的：提供一种半导体器件及其制造方法，以通过在单元区域或划线中形成虚拟通孔电极来提高机械接合强度，以获得并联电连接。 构成：在衬底（107）中制备具有衬垫（110）的细胞区域（105）和限定细胞区域的划线通道区域（106）。 通孔电极（160）与焊盘电连接。 虚拟通电极（170）与通孔电连接。 导电图案（152）与通孔电极和虚拟通孔电连接。 钝化层（140）保护衬底的前侧（102）。
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