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公开(公告)号：KR1020090089075A
公开(公告)日：2009-08-21
申请号：KR1020080014423
申请日：2008-02-18
Applicant: 삼성전자주식회사
IPC: G11C16/04
CPC classification number: G11C16/06 , G06F12/0246 , G11C11/5628
Abstract: A nonvolatile memory device is provided to control the performance and capacitance according to the purpose of a user by controlling the size of a first logic volume and a second logic volume dynamically. A non-volatile memory device includes a nonvolatile memory cell array, a controller(450), and a user interface(470). The non-volatile memory device includes two bit multi-level cells. The nonvolatile memory cell array is divided into the first logic volume and the second logic volume. The first logic volume uses one bit for writing and reading. The second logic volume uses two bits for writing and reading. The controller dynamically determines the volume of the first and second logic volume according to the selection of the user. The user selects the size of the first and second logic volumes.
Abstract translation: 提供非易失性存储器件，用于通过动态地控制第一逻辑卷和第二逻辑卷的大小来根据用户的目的来控制性能和电容。 非易失性存储器件包括非易失性存储单元阵列，控制器（450）和用户界面（470）。 非易失性存储器件包括两位多电平单元。 非易失性存储单元阵列被分成第一逻辑卷和第二逻辑卷。 第一个逻辑卷使用一个位进行写入和读取。 第二个逻辑卷使用两位写入和读取。 控制器根据用户的选择动态地确定第一和第二逻辑卷的音量。 用户选择第一和第二逻辑卷的大小。
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公开(公告)号：KR1019980003851A
公开(公告)日：1998-03-30
申请号：KR1019960021025
申请日：1996-06-12
Applicant: 삼성전자주식회사
IPC: H01L21/027
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公开(公告)号：KR1019970006976B1
公开(公告)日：1997-05-01
申请号：KR1019930028898
申请日：1993-12-21
Applicant: 삼성전자주식회사
IPC: H01L29/68
Abstract: A semiconductor device is described that can reduce surface electric field. The semiconductor device includes a semiconductor substrate comprised of collector regions 31 and 33 which is highly and lightly doped with N-type dopant, respectively, a base region 35 formed by the diffusion in the collector region 33, an emitter region 39 formed by the diffusion in the base region 35, a field limiting ring 37 formed by the diffusion to surround the base region 35, a channel stopper 41 formed by the diffusion in the collector region 33, insulating layers 43 and 45 formed over regions except the base region 35, emitter region 39 and channel stopper 41, forming collector electrode 49, base electrode 47, emitter electrode 48 and equal voltage electrode 53, and forming a field electrode 51 over the insulating layer 45. Thereby, it is possible to improve the characteristic of resisting pressure.
Abstract translation: 描述了可以减少表面电场的半导体器件。 半导体器件包括由集电极区域31和33分别构成的半导体衬底，其分别高度轻掺杂有N型掺杂剂，通过在集电极区域33中的扩散形成的基极区域35，由扩散形成的发射极区域39 在基极区域35中，通过扩散形成的围绕基极区域35的场限制环37，在集电极区域33内扩散形成的沟道阻挡层41，形成在基极区域35以外的区域的绝缘层43,45， 发射极区域39和通道阻挡器41，形成集电极49，基极电极47，发射极电极48和等压电极53，并且在绝缘层45上形成场电极51.由此，可以提高耐压力的特性 。
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公开(公告)号：KR1019950021725A
公开(公告)日：1995-07-26
申请号：KR1019930028898
申请日：1993-12-21
Applicant: 삼성전자주식회사
IPC: H01L29/68
Abstract: 본 발명은 고내압반도체장치에 관한 것으로, 저농도콜렉터 영역에 베이스역을 에워싸 형성된 필드리미팅링의 상부에 필드전극이 저농도콜렉터영역의 상부에 형성된 절연막에 의해 상기 필드리미팅과 접촉되지 않도록 베이스전극, 에미터전극 및 등전위전극과 동시에 헝성된다. 따라서 필드전극을 절연막의 상부에 필드리미팅링과 접촉되지 않도록 형성되므로 필드리미팅링의 표면이 오염되는 것을 방지할 수 있으며 표면전체를 감소시켜 내압 특성을 안정시킬 수 있고, 또한, 필드전극이 베 이스전극, 에미터전극 및 등전위전극과 동시에 형성되므로 제조가 간단하다.
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公开(公告)号：KR1019940001259B1
公开(公告)日：1994-02-18
申请号：KR1019910013490
申请日：1991-08-03
Applicant: 삼성전자주식회사
IPC: H01L29/732
Abstract: The P-type base area (13) is formed on substrates (11,12) by a diffusion process. An isolating area (61) is made to cover a low density layer (12) which is fabricated on a high density layer (11), and to be atched for electrodes (41,42,43,44,45,46,47). Emitters (21,22,23) which are formed at the inside of a P-type base area (13) have a ring type structure.
Abstract translation: 通过扩散处理在基板（11,12）上形成P型基底区域（13）。 隔离区域（61）被制成覆盖制造在高密度层（11）上的低密度层（12），并且用于电极（41,42,43,44,45,46,47） 。 在P型基部区域（13）的内侧形成的发射体（21,22,23）具有环型结构。
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Patent Agency Ranking
公开(公告)号：KR102057030B1
公开(公告)日：2019-12-18
申请号：KR1020130094979
申请日：2013-08-09
Applicant: 삼성전자주식회사
IPC: H01L21/301 , H01L21/336 , H01L29/78 , H01L21/31
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公开(公告)号：KR102021887B1
公开(公告)日：2019-09-17
申请号：KR1020130152569
申请日：2013-12-09
Applicant: 삼성전자주식회사
IPC: H01L29/778 , H01L21/335
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