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公开(公告)号：KR1020150144545A
公开(公告)日：2015-12-28
申请号：KR1020140073433
申请日：2014-06-17
Applicant: 삼성전자주식회사
CPC classification number: G06F3/0673 , G06F3/061 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F12/0866 , G06F2212/1016
Abstract: 본발명의실시예에따른메모리컨트롤러의작동방법은호스트로부터라이트명령이입력될때마다새로운엔트리를할당하는단계와, 상기호스트로부터출력된리드명령에응답하여복수의상태들중 특정상태를갖는엔트리에해당하는데이터를상기호스트로전송하는단계를포함한다. 상기할당하는단계는제1LBA(logical block address)와제1데이터를포함하는제1라이트명령에제1엔트리를할당하는단계와, 제2LBA와제2데이터를포함하는제2라이트명령에제2엔트리를할당하는단계를포함한다. 상기제1LBA와상기제2LBA는서로동일할수 있다.
Abstract translation: 根据本发明的实施例，用于操作存储器控制器的方法包括以下步骤：每当从主机输入写入命令时，分配一个新条目; 以及通过响应从主机输出的读取命令向主机发送与多个状态中具有一定状态的条目相对应的数据。 分配步骤包括：将第一条目分配给包括第一逻辑块地址（LBA）和第一数据的第一写入命令; 以及将第二条目分配给包括第二逻辑块地址（LBA）的第二写入命令。 第一个LBA和第二个LBA可能彼此相等。
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公开(公告)号：KR101543246B1
公开(公告)日：2015-08-11
申请号：KR1020090035962
申请日：2009-04-24
Applicant: 삼성전자주식회사
CPC classification number: G06F12/0607 , G06F12/0246 , G06F2212/7208
Abstract: 데이터저장장치의동작방법이제공된다. 데이터저장장치의동작방법은, 데이터신호와함께입력된데이터신호의논리어드레스에기초하여비순차적채널분배방식으로채널분배를수행하고채널어드레스를출력하는단계및 다수의채널들중에서채널어드레스에의하여지정된하나의채널에접속된메모리에데이터신호를라이트하는단계를포함한다.
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公开(公告)号：KR101347285B1
公开(公告)日：2014-01-07
申请号：KR1020070098360
申请日：2007-09-28
Applicant: 삼성전자주식회사
CPC classification number: G06F12/0862 , G06F12/0866 , G06F12/0897 , G06F2212/221 , G06F2212/222
Abstract: 본 발명은 하드디스크 드라이브의 선반입 방법, 이에 적합한 기록 매체 그리고 이에 적합한 장치에 관한 것으로, 본 발명에 따른 하드디스크 드라이브의 선반입 방법에 있어서, 외부장치로부터 요청받은 데이터의 논리적 블록 주소가 비휘발성 캐쉬의 히스토리에 저장되어 있는지 탐색하는 단계; 및 요청된 데이터의 LBA가 히스토리에 저장되어 있는 경우, 히스토리에 저장되어 있는 LBA들 중에서, 요청된 데이터의 LBA의 다음 순서로 저장된 LBA에 기록된 데이터를 버퍼에 저장하는 단계를 포함한다.
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公开(公告)号：KR1020100130007A
公开(公告)日：2010-12-10
申请号：KR1020090048650
申请日：2009-06-02
Applicant: 삼성전자주식회사
CPC classification number: G06F12/0246 , G06F2212/7201
Abstract: PURPOSE: A data storing device is provided to effectively combine data having continuous logical address and a discontinuous physical address among data stored in blocks, thereby improving performance of reading and writing data. CONSTITUTION: A least one memory chips includes a plurality of blocks(210) and a control unit(250). At least one memory chip communicates with a host through the same channel. A memory stores an output data of the memory chip. The control unit successively reads data having continuous logical address and discontinuous physical address among data stored in the blocks. To enable the data to have the continuous physical address, the control unit stores the data to the memory.
Abstract translation: 目的：提供数据存储装置，以有效地组合存储在块中的数据之间具有连续逻辑地址和不连续物理地址的数据，从而提高读写数据的性能。 构成：至少一个存储器芯片包括多个块（210）和控制单元（250）。 至少一个存储器芯片通过相同的通道与主机通信。 存储器存储存储器芯片的输出数据。 控制单元连续读取在块中存储的数据中具有连续逻辑地址和不连续物理地址的数据。 为了使数据具有连续的物理地址，控制单元将数据存储到存储器中。
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公开(公告)号：KR1020100117295A
公开(公告)日：2010-11-03
申请号：KR1020090035962
申请日：2009-04-24
Applicant: 삼성전자주식회사
CPC classification number: G06F12/0607 , G06F12/0246 , G06F2212/7208
Abstract: PURPOSE: A method for driving a data storage device and the data storage device thereof are provided to improve the performance of a data storage device by distributing the plural page of the data storage device based on a non-sequential channel distribution algorithm. CONSTITUTION: Memories are connected to channels(135). A distribution unit(133) performs channel distribution based on a non-sequential channel distribution scheme by considering a logical address inputted from a host and outputs a channel address. A read/write module(131) performs address mapping based on the channel address to record a data signal inputted from the host to a memory connected to a channel designated by the channel address.
Abstract translation: 目的：提供一种用于驱动数据存储设备及其数据存储设备的方法，用于通过基于非顺序信道分布算法分布数据存储设备的多页来提高数据存储设备的性能。 构成：回忆连接到频道（135）。 分发单元（133）通过考虑从主机输入的逻辑地址来执行基于非顺序信道分配方案的信道分发并输出信道地址。 读/写模块（131）基于通道地址执行地址映射，以将从主机输入的数据信号记录到连接到由通道地址指定的通道的存储器。
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Patent Agency Ranking
公开(公告)号：KR1020100033855A
公开(公告)日：2010-03-31
申请号：KR1020080092920
申请日：2008-09-22
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5628 , G11C29/00
Abstract: PURPOSE: An LSB(Least Significant Bit) page recovering method is provided to easily restore a LSB page in case that an electric power supply is shut down in the process of a program for a MSB(Most Significant Bit) page. CONSTITUTION: A first LSB page group or an n-th LSB page group which include at least two LSB pages are set. A first LSB page or an x-th LSB page which are included in an i-th LSB page group are programmed. An i-th LSB parity page for the first LSB page or the x-th LSB page is generated. A first MSB page or an x-th MSB page corresponding to one LSB page is programmed. A j-th LSB page which pairs with a j-th MSB page is restored by using the i-th LSB parity page in the inactive state of the power supply.
Abstract translation: 目的：提供LSB（最低有效位）页面恢复方法，以便在MSB（最高有效位）页面的程序过程中关闭电源的情况下轻松恢复LSB页面。 构成：设置包括至少两个LSB页的第一LSB页组或第n LSB页组。 包含在第i个LSB页组中的第一LSB页或第x个LSB页被编程。 产生第一LSB页或第LSB LSB页的第i个LSB奇偶校验页。 对应于一个LSB页面的第一个MSB页面或第x个MSB页面被编程。 通过使用处于电源的非活动状态的第i个LSB奇偶校验页来恢复与第j个MSB页对应的第j个LSB页。
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公开(公告)号：KR1020090089075A
公开(公告)日：2009-08-21
申请号：KR1020080014423
申请日：2008-02-18
Applicant: 삼성전자주식회사
IPC: G11C16/04
CPC classification number: G11C16/06 , G06F12/0246 , G11C11/5628
Abstract: A nonvolatile memory device is provided to control the performance and capacitance according to the purpose of a user by controlling the size of a first logic volume and a second logic volume dynamically. A non-volatile memory device includes a nonvolatile memory cell array, a controller(450), and a user interface(470). The non-volatile memory device includes two bit multi-level cells. The nonvolatile memory cell array is divided into the first logic volume and the second logic volume. The first logic volume uses one bit for writing and reading. The second logic volume uses two bits for writing and reading. The controller dynamically determines the volume of the first and second logic volume according to the selection of the user. The user selects the size of the first and second logic volumes.
Abstract translation: 提供非易失性存储器件，用于通过动态地控制第一逻辑卷和第二逻辑卷的大小来根据用户的目的来控制性能和电容。 非易失性存储器件包括非易失性存储单元阵列，控制器（450）和用户界面（470）。 非易失性存储器件包括两位多电平单元。 非易失性存储单元阵列被分成第一逻辑卷和第二逻辑卷。 第一个逻辑卷使用一个位进行写入和读取。 第二个逻辑卷使用两位写入和读取。 控制器根据用户的选择动态地确定第一和第二逻辑卷的音量。 用户选择第一和第二逻辑卷的大小。
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公开(公告)号：KR1020160072882A
公开(公告)日：2016-06-24
申请号：KR1020140180342
申请日：2014-12-15
Applicant: 삼성전자주식회사
CPC classification number: G11C16/16 , G11C7/02 , G11C7/04 , G11C16/0483 , G11C16/26 , G11C16/32 , G11C16/3404 , G11C16/06 , G11C16/10 , G11C16/14 , G11C16/30
Abstract: 본발명은복수의메모리셀들을포함하는불휘발성메모리및 불휘발성메모리를제어하는메모리컨트롤러를포함하는스토리지장치의동작방법에관한것이다. 본발명의동작방법은, 불휘발성메모리의복수의메모리셀들중 미리프로그램된메모리셀들을읽어, 미리프로그램된메모리셀들의소거후 경과시간을계산하는단계, 불휘발성메모리의선택된메모리셀들을프로그램하는단계, 그리고계산된소거후 경과시간에기반하여, 선택된메모리셀들의소거후 경과시간을포함하는메타데이터를불휘발성메모리에프로그램하는단계로구성된다.
Abstract translation: 本发明涉及一种操作包括包括多个存储单元的非易失性存储器和用于控制非易失性存储器的存储器控制器的存储设备的方法。 根据本发明的方法包括以下步骤：读取在非易失性存储器的多个存储单元中预先编程的存储器单元，并且计算在预先编程的存储器单元被擦除之后的经过时间，编程所选择的非易失性存储单元 存储器，基于擦除之后计算出的经过时间，包括擦除非易失性存储器中的存储器单元之后的经过时间的元数据。 根据本发明的实施例，测量在存储单元被擦除之后存储单元被编程之前的经过时间。
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公开(公告)号：KR101541736B1
公开(公告)日：2015-08-04
申请号：KR1020080092920
申请日：2008-09-22
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5628 , G11C29/00
Abstract: 멀티-레벨셀 플래시메모리장치에서의 LSB 페이지복구방법이개시된다. 본발명의실시예에따른 LSB 페이지와 MSB 페이지가페어드페이지(paired page) 구조로쌍을이루어프로그램또는독출되는멀티-레벨셀 플래시메모리에서의 LSB 페이지복구방법에있어서, 각각, 상기멀티-레벨셀 플래시메모리의 LSB 페이지들중 적어도둘 이상의 LSB 페이지를포함하는제1 LSB 페이지그룹내지제n(n은 2 이상의자연수) LSB 페이지그룹들을설정하는단계; 제i(i는 n 이하의자연수) LSB 페이지그룹에속하는제1 LSB 페이지내지제x(x는 2 이상의자연수) LSB 페이지들을프로그램하는단계; 상기제1 LSB 페이지내지상기제x LSB 페이지들에대한제i LSB 패리티(parity) 페이지를생성하고저장하는단계; 각각, 상기제1 LSB 페이지내지상기제x LSB 페이지들중 하나의 LSB 페이지에대응되는제1 MSB 페이지내지제x MSB 페이지를프로그램하는단계; 및제j(j는 x 이하의자연수) MSB 페이지를프로그램하는중에상기멀티-레벨셀 플래시메모리로의전원공급이차단되는경우, 상기제i LSB 패리티페이지를이용하여상기제j MSB 페이지와쌍을이루는제j LSB 페이지를복구하는단계를구비한다.
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公开(公告)号：KR1020130010731A
公开(公告)日：2013-01-29
申请号：KR1020110071547
申请日：2011-07-19
Applicant: 삼성전자주식회사
CPC classification number: G06F12/0246 , G06F2212/7202 , G06F2212/7208 , G11C29/82
Abstract: PURPOSE: A memory device is provided to prevent response time delay about a request of a host by processing a valid page of a defect block in idle time. CONSTITUTION: A control unit manages a global reserved area, a first virtual area about a first memory chip, and a second virtual area about a second memory chip. The first virtual area includes a first user area and a first reserved area. The second virtual area includes a second user area and a second reserved area. The global reserved area includes first reserved blocks and second reserved blocks. If a first virtual block is detected to a bad block, the control unit allocates a second virtual block to the first user area.
Abstract translation: 目的：提供一种存储设备，通过在空闲时间内处理缺陷块的有效页面来防止关于主机请求的响应时间延迟。 构成：控制单元管理全局保留区域，关于第一存储器芯片的第一虚拟区域和关于第二存储器芯片的第二虚拟区域。 第一虚拟区域包括第一用户区域和第一保留区域。 第二虚拟区域包括第二用户区域和第二保留区域。 全局保留区包括第一保留块和第二保留块。 如果第一虚拟块被检测到坏块，则控制单元将第二虚拟块分配给第一用户区。
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