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公开(公告)号：KR100377197B1
公开(公告)日：2003-03-26
申请号：KR1020000082253
申请日：2000-12-26
Applicant: 한국전자통신연구원
IPC: H04B1/16
CPC classification number: H04L5/06 , H04B1/7115
Abstract: In the apparatus and method for separating carrier of multicarrier wireless communication receiver system, each carrier separation is performed after a quantization in a wireless communication receiver system such as a received multicarrier CDMA (Code Division Multiple Access) etc., to thereby reduce the whole number of quantizers and separate multicarrier from a received signal. For that, the apparatus for separating the carrier of the multicarrier wireless communication receiver system includes an internal oscillating unit for generating internal multicarrier; a plurality of frequency transition units for respectively down-converting the multicarrier generated by the internal oscillating unit and moving it to frequency of "0" as a frequency center; and a plurality of filtering units for individually filtering the respective carrier moved by the plurality of frequency transition units to the frequency center as the frequency of "0", through a low frequency pass band and for providing it as an input of a rake receiver.
Abstract translation: 在用于多载波无线通信接收机系统的载波分离的设备和方法中，在诸如接收到的多载波CDMA（码分多址）等的无线通信接收机系统中进行量化之后执行每个载波分离，从而减少整数 量化器和独立的多载波与接收信号。 为此，用于分离多载波无线通信接收机系统的载波的设备包括：用于生成内部多载波的内部振荡单元; 多个频率转换单元，用于分别下转换由内部振荡单元产生的多载波并将其移动到“0”的频率; 作为一个频率中心; 以及多个滤波单元，用于通过低频通带将由多个频率转换单元移动的相应载波单独滤波到作为频率“0”的频率中心，并用于将其提供为瑞克接收机的输入 。
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公开(公告)号：KR1020020032157A
公开(公告)日：2002-05-03
申请号：KR1020000063098
申请日：2000-10-26
Applicant: 한국전자통신연구원
IPC: H03H17/06
CPC classification number: H03H17/0607 , H03H17/0226 , H03H17/0621 , H03H17/0657
Abstract: PURPOSE: A finite impulse response filter without using multiplier is provided to process an FIR filter operation a look-up table method suitable in a high speed operation without using a multiplier. CONSTITUTION: An input shift register and selector(100) shifts and stores 4 bit filter input, and selects one among the stored input data in response to a clock signal. An address generator(200) generates an address suited to a look-up table of each counting group in response to the data from the input shift register and selector(100). Look-up table groups 0, 3, 1, and 2(300,400,500,600) receive an address of a corresponding group from the address generator(200) and generate a filter output corresponding to the address by a look-up table. Integrator group 0, 3, 1, and 2(700.800,900,1000) shift and integrate results outputted by each counting groups by an input bit number. 4x1 multiplexor(1100) serially outputs of the integrator group 0, 3, 1, and 2(700.800,900,1000) in response to a control signal.
Abstract translation: 目的：提供一种不使用乘法器的有限脉冲响应滤波器来处理FIR滤波器操作，适用于高速运行的查找表方法，而不使用乘法器。 构成：输入移位寄存器和选择器（100）移位并存储4位滤波器输入，并根据时钟信号选择存储的输入数据之一。 响应于来自输入移位寄存器和选择器（100）的数据，地址发生器（200）产生适合于每个计数组的查找表的地址。 查找表组0,3,1和2（300,400,500,600）从地址生成器（200）接收相应组的地址，并通过查找表生成对应于地址的过滤器输出。 积分器组0,3,1和2（700.800,900,1000）将每个计数组输出的结果移位并整合输入位数。 4×1多路复用器（1100）响应于控制信号串行输出积分器组0,3,1和2（700.800,900,1000）。
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公开(公告)号：KR1020020010845A
公开(公告)日：2002-02-06
申请号：KR1020000044405
申请日：2000-07-31
Applicant: 한국전자통신연구원
IPC: H04L27/30
CPC classification number: H03H17/0621 , H03H17/0607
Abstract: PURPOSE: A 108 tap 1:4 interpolation finite impulse response filter device for digital mobile communication is provided to be capable of simultaneously performing 4 filter operations without increasing the speed of operation frequency by applying a pipeline technique and a look-up table technique. CONSTITUTION: An input shift register and selector(100) shifts bit filter inputs and outputs 27-bit parallel data, and sequentially the output parallel data one by one. An address generator(200) receives the 27-bit parallel data to generate addresses according to respective counting groups. Look-up table groups(300,400,500,600) generate the filter outputs of count groups by using the addresses generated in the address generator. A pipeline register(700) delays the filter outputs per count group output in parallel from the look-up table groups. A group selector(800) converts the outputs delayed from the pipeline register(700) into DC outputs. A pipeline register(900) delays the outputs of the group selector to match the filter output times of respective channels.
Abstract translation: 目的：提供一种用于数字移动通信的108抽头1：4内插有限脉冲响应滤波器装置，可以通过应用流水线技术和查找表技术，同时执行4个滤波操作而不增加操作频率。 构成：输入移位寄存器和选择器（100）将位滤波器输入和输出移位27位并行数据，并逐个依次输出并行数据。 地址发生器（200）接收27位并行数据，以根据各个计数组产生地址。 查询表组（300,400,500,600）通过使用地址生成器中生成的地址生成计数组的过滤器输出。 流水线寄存器（700）从查找表组并行延迟每个计数组输出的滤波器输出。 组选择器（800）将从流水线寄存器（700）延迟的输出转换成直流输出。 流水线寄存器（900）延迟组选择器的输出以匹配各个通道的滤波器输出时间。
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公开(公告)号：KR1020010009726A
公开(公告)日：2001-02-05
申请号：KR1019990028261
申请日：1999-07-13
IPC: H03M13/00
CPC classification number: H03M13/2732 , H03M13/6502
Abstract: PURPOSE: A channel encoder for the digital communication is provided to carry out a convolutional-encoding and an interleaving operation at once by using two LAMs for buffering a frame input data having the low memory usage alternately. CONSTITUTION: The device carries out a convolutional-encoding and interleaving operation of a frame input data at once by using two encoder RAMs(417). A microcontroller controls to store a frame input data input to a frame input data register(411) into the first encoder RAM(416) while parallel-inputs into a parallel CRC generator(412) generated by the number of a given CRC input bit and a production polynomial. A device carries out an XOR logic-operation of the input parallel CRC input value and the previous CRC state value to parallel calculate a desired CRC output value. A device stores the CRC output value with the frame data stored in the first encoder RAM and reads the stored CRC output value to carry out the convolutional encoding and the interleaving. The convolutional encoding and interleaving for the frame input data, and storing the next frame input data into the second encoder RAM are carried out at once.
Abstract translation: 目的：提供用于数字通信的信道编码器，通过使用两个LAM来交替地缓冲具有低存储器使用的帧输入数据来一次执行卷积编码和交织操作。 构成：该装置通过使用两个编码器RAM（417）一次执行帧输入数据的卷积编码和交织操作。 微控制器控制将输入到帧输入数据寄存器（411）的帧输入数据存储到第一编码器RAM（416）中，同时并入输入到由给定CRC输入位的数量产生的并行CRC生成器（412） 一个生产多项式。 设备执行输入并行CRC输入值和先前CRC状态值的异或逻辑运算，以并行计算所需的CRC输出值。 设备将CRC输出值与存储在第一编码器RAM中的帧数据进行存储，并读出所存储的CRC输出值，以执行卷积编码和交织。 帧输入数据的卷积编码和交织，并将下一帧输入数据存储到第二编码器RAM中一次进行。
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公开(公告)号：KR1019980043601A
公开(公告)日：1998-09-05
申请号：KR1019960061528
申请日：1996-12-04
Applicant: 한국전자통신연구원
IPC: H03K23/00
Abstract: 본 발명은 디지털 회로로 구성된 2.5 분주장치에 관한 것이다. 그 목적은 카운터 및 간단한 디지털 논리소자를 사용하여 2.5 분주장치를 집적회로 내에 구현하는데에 있다. 그 구성은 클럭을 입력받아 카운팅을 수행하는 카운팅수단과, 파워-온 리셋을 입력받고 나서 클럭에 동기시켜 카운팅 수단을 리셋하거나 카운팅 수단이 소정의 조건을 만족하면서 카운팅 수단을 리셋하는 리셋수단과, 카운팅 수단의 출력을 사용하여 원하는 클럭 라이징인 제1클럭을 생산하는 제1클럭생성 수단과, 제1클럭을 입력클럭의 1/4 주기만큼 지연시켜 제2클럭을 생성하는 제2클럭생성 수단 및 제1클럭과 제2클럭을 입력받아 2.5분주된 클럭을 출력하는 출력수단으로 되어 있다.
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Patent Agency Ranking
公开(公告)号：KR1019960027294A
公开(公告)日：1996-07-22
申请号：KR1019940036350
申请日：1994-12-23
Applicant: 한국전자통신연구원
Abstract: 본 발명은 디지틀 신호를 펄스폭 변조신호로 변환하는 장치에 관한 것으로, 계수기(20)를 이용하여 증가하는 방향으로 계수하여 이 결과를 변형회로(30)를 거쳐 계수기 신호를 변환하고 바꾸고자하는 디지틀 값이 저장되어 있는 레지스터의 값에 의해 제어되어 원하는 펄스폭 변조신호가 생성된다.
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公开(公告)号：KR1019960008222B1
公开(公告)日：1996-06-20
申请号：KR1019930027856
申请日：1993-12-15
Applicant: 한국전자통신연구원
IPC: H03H17/00
Abstract: two T/N bit shift registers (23,24) which input I_ data and Q_ data by CK(2N)B; two T/2N bit MUX (25,26) which input I_ data and Q_ data into the addresses of the integrating coefficient ROM; two integrating coefficient ROM (27,28) which store the result of integrating subgroup N, N*2T/2N; a (B+1) bit adder (29) which adds the output of the ROM (27,28); a A bit register (30) which stores the output of the (B+1) bit adder (29) by CK1B; a CK1,which is the system clock of CDMA base division.
Abstract translation: 两个T / N位移位寄存器（23,24），其通过CK（2N）B输入I_数据和Q_数据; 将I_数据和Q_数据输入到积分系数ROM的地址的两个T / 2N位MUX（25,26） 存储积分子组N，N * 2T / 2N的结果的两个积分系数ROM（27,28）; 一个加上ROM（27,28）的输出的（B + 1）位加法器（29）; 存储（B + 1）位加法器（29）的输出由CK1B存储的A位寄存器（30） 一个CK1，它是CDMA基站的系统时钟。
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公开(公告)号：KR1019950005243B1
公开(公告)日：1995-05-22
申请号：KR1019920025399
申请日：1992-12-24
IPC: G06F12/02
Abstract: The method efficiently reduces the algorithm executing time by DSP usage. It employs a registers(10) which reduces the address, the 1st counter(50) which decreases the address by 1 step, the 2nd counter(60) which executes the command execution, a buffer(80) which saves the address, the 1st multiplexer(20) which gives the address to one of registers,a databus(90), the 2nd multiplexer(40) which gives the repeating information to the 1st counter(50), and the 3rd multiplexer(70) which makes the buffer addressable.
Abstract translation: 该方法通过DSP使用有效地减少了执行算法的时间。 它采用减少地址的寄存器（10），减少地址的第一计数器（50）1步，执行命令执行的第二计数器（60），保存地址的缓冲器（80），第1 将地址给予寄存器之一的多路复用器（20），向第一计数器（50）提供重复信息的数据总线（90），第二多路复用器（40）和使缓冲器可寻址的第三多路复用器（70） 。
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