公开(公告)号：WO1997020272A1

公开(公告)日：1997-06-05

申请号：PCT/US1996016493

申请日：1996-10-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LONGWELL, Michael, L. ,  GEISLER, Joseph, P.

IPC: G06F13/40

CPC classification number: G06F13/4077

Abstract: An apparatus is provided for precharging a conductor within a bus containing a plurality of conductors. The apparatus comprises a precharge driver which precharges alternating pairs of conductors to opposite rail voltages. By precharging pairs of conductors to alternating rails, the present apparatus can minimize the speed degradation problems associated with a transitioning target conductor within the bus. Precharging alternating pairs of conductors also minimizes crosstalk noise from transitioning neighbor conductors to a non-transitioning target conductor. The improved dynamic bus thereby demonstrates improvements in speed degradation and crosstalk noise as seen by a transitioning target conductor or non-transitioning target conductor, respectively.

Abstract translation: 提供一种用于对包含多个导体的总线内的导体进行预充电的装置。 该装置包括预充电驱动器，其将交替的导线对预充电到相对的导轨电压。 通过将成对的导体预先充电到交替的轨道，本装置可以最小化与总线内的转换目标导体相关联的速度退化问题。 对交替的导线对进行预充电还可以将从相邻的导体过渡到非转换的目标导体的串扰噪声最小化。 因此，改进的动态总线显示出分别由转换目标导体或非转换目标导体看到的速度劣化和串扰噪声的改进。

公开(公告)号：WO1997019510A1

公开(公告)日：1997-05-29

申请号：PCT/US1996012125

申请日：1996-07-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CLEVELAND, Lee, E.

IPC: H02M03/07

CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/07

Abstract: A voltage booster circuit includes a driver circuit (117) for generating a 3-state output for driving wordlines via row decoder circuits in an array of flash EEPROM memory cells during read and programming modes of operation. The driver circuit effectively disconnects a large booster capacitor (115) in order to allow a small charge pump (114) to further pump up the wordline voltage during programming. As a result, the booster pump has improved efficiency since there is achieved a significant reduction in power consumption.

Abstract translation: 升压电路包括驱动电路（117），用于在读取和编程操作模式期间，通过行闪存EEPROM存储器单元阵列中的行解码器电路产生用于驱动字线的3态输出。 驱动器电路有效地断开大型升压电容器（115），以便在编程期间允许小电荷泵（114）进一步泵送字线电压。 结果，由于实现了功率消耗的显着降低，所以增压泵具有提高的效率。

公开(公告)号：WO1997019453A1

公开(公告)日：1997-05-29

申请号：PCT/US1996014936

申请日：1996-09-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  PENG, Jack, Zezhong

IPC: G11C16/04

CPC classification number: G11C16/0433 ,  G11C16/0441

Abstract: A memory cell for a programmable logic device (PLD) and method for programming the memory cell. The memory cell includes components typically found in a memory cell for a PLD including an NMOS transistor having a floating gate, and two capacitors coupled to the floating gate, one capacitor being a tunneling capacitor enabling charge to be added to and removed from the floating gate. The memory cell further includes an NMOS pass gate transistor for supplying charge to the tunneling capacitor, but unlike conventional NMOS pass gates, it has a reduced threshold so that during programming when a programming voltage is applied to its drain, it can be turned on with an identical programming voltage applied to its gate, rather than requiring that its gate voltage be pumped above its drain voltage during programming. The reduced threshold can be obtained by removing the vt implant and punch through implant normally provided in its channel, or by other means.

Abstract translation: 用于可编程逻辑器件（PLD）的存储器单元和用于对存储器单元进行编程的方法。 存储单元包括通常存在于用于PLD的存储器单元中的组件，其包括具有浮置栅极的NMOS晶体管，以及耦合到浮置栅极的两个电容器，一个电容器是隧穿电容器，其使得能够将电荷加到浮栅 。 存储单元还包括用于向隧道电容器提供电荷的NMOS栅极晶体管，但是与传统的NMOS栅极不同，它具有降低的阈值，使得在将编程电压施加到其漏极的编程期间，可以用 施加到其栅极的相同的编程电压，而不是要求其编程期间将其栅极电压泵送到其漏极电压以上。 减少的阈值可以通过去除vt植入物并穿过正常设置在其通道中的植入物或通过其他方式来获得。

公开(公告)号：WO1997017788A1

公开(公告)日：1997-05-15

申请号：PCT/US1996011850

申请日：1996-07-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GREEN, Patrick ,  RUNALDUE, Jeffrey ,  BIANCHINI, Ronald, Jr.

IPC: H04L12/56

CPC classification number: H04L12/5601 ,  H04L49/106 ,  H04L49/1553 ,  H04L49/1561 ,  H04L49/203 ,  H04L2012/5651 ,  H04L2012/5681

Abstract: An ATM switch with multicast capability uses a feedback mechanism for resolving contentions. A multicast network reads N cells from an input queue, replicates multicast cells and translates their addresses in accordance with an external look-up table. The processed N cells are stored in a temporary buffer until information regarding the number (F) of cells fed back due to contention in the previous switching cycle is available. A rotator positions N-F cells from the temporary buffer on inputs of an output network so as to assign the cells from the temporary buffer a lower priority than a priority of the feed back cells. The output network selects the cells that can be switched to their destinations and transfers them to output ports. The cells that cannot be switched due to contention are fed back to be presented for the output network consideration in the next switching cycle. At the same time, a pointer of the input queue is decremented by a factor depending on the number of feedback cells, and the number of multicast and unicast cells in the current switching cycle.

Abstract translation: 具有组播功能的ATM交换机使用反馈机制来解决争用。 组播网络从输入队列中读取N个单元，根据外部查找表复制多播单元并翻译其地址。 处理的N个单元被存储在临时缓冲器中，直到有关由于在前一个切换周期中的争用而被反馈的单元的数量（F）的信息可用。 旋转器将来自临时缓冲器的N-F个单元从输出网络的输入端定位，从而将来自临时缓冲器的单元分配给比反馈单元优先级低的优先级。 输出网络选择可以切换到目的地的单元，并将其传输到输出端口。 反馈由于竞争而不能切换的单元被反馈以在下一个切换周期中呈现用于输出网络的考虑。 同时，输入队列的指针根据反馈单元的数量以及当前切换周期中的组播和单播小区的数量而减少。

公开(公告)号：WO1997015881A1

公开(公告)日：1997-05-01

申请号：PCT/US1996016461

申请日：1996-10-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  PALANISWAMI, Krishnan

IPC: G06F09/22

CPC classification number: G06F9/223 ,  G06F9/30145 ,  G06F9/30196

Abstract: A digital signal controller is provided having modular operation. Specifically, the digital signal controller includes a sequence control unit and a sequencer for producing a sequence of macro instructions and a sequence of micro instructions, respectively. Changes in the number or order of macro instructions may not require changes to the number and order of micro instructions and vice versa. As such, changes in macro instructions can occur by modifying the sequence control unit and possibly the decoder without necessarily changing the sequencer. Changes in the number and order of micro instructions require changes in the sequencer and possibly the decoder without necessarily changing the sequence control unit. The aforementioned modular technique of forwarding macro and micro instructions to a decoder for controlling an execution unit arranged between an analog interface unit and a DSP allows variability in the operation of the DSP, as well as variability in the design implementation of changes to the digital signal controller.

Abstract translation: 提供具有模块化操作的数字信号控制器。 具体地，数字信号控制器包括分别用于产生宏指令序列和微指令序列的序列控制单元和定序器。 宏指令的数量或顺序的更改可能不需要更改微指令的数量和顺序，反之亦然。 这样，可以通过修改序列控制单元和可能的解码器而不必改变定序器来发生宏指令的改变。 微指令的数量和顺序的变化需要定序器和可能的解码器的改变，而不必改变顺序控制单元。 将宏指令和微指令转发到用于控制布置在模拟接口单元和DSP之间的执行单元的解码器的上述模块化技术允许DSP的操作变化，以及数字信号变化的设计实现的变化性 控制器。

公开(公告)号：WO1997013196A1

公开(公告)日：1997-04-10

申请号：PCT/US1996015740

申请日：1996-10-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  FAVOR, John, G.

IPC: G06F09/318

CPC classification number: G06F9/382 ,  G06F9/30054 ,  G06F9/30152 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3806 ,  G06F9/3812 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3853

Abstract: An instruction decoder (220) includes an emulation code sequencer (510) and emulation code ROM (520) for handling various instructions. The emulation code ROM includes a sequence of operations (Op) and an operation sequencing control code (OpSeq). Branch instructions such as conditional branch instructions may be encoded into the emulation code ROM so that a second branch, in combination with the branching operation controlled by the OpSeq code, is applied to an operation code sequence. Two-way branching permits flexible branching to locations within the emulation code ROM so that memory capacity is conserved. A superscalar microprocessor (120) includes an instruction decoder having an emulation code control circuit and an emulation ROM which emulates the function of a logic instruction decoder. The emulation code ROM is arranged as a matrix of multiple-operation (Op) units with each multiple-Op unit including a control field that points to a next location in the emulation code ROM. In one embodiment, the emulation code ROM is arranged to include a plurality of four-Op units, called Op quads, with each Op quad including a sequencing control field, called an OpSeq field.

Abstract translation: 指令解码器（220）包括用于处理各种指令的仿真代码定序器（510）和仿真代码ROM（520）。 仿真代码ROM包括操作序列（Op）和操作顺序控制代码（OpSeq）。 诸如条件分支指令之类的分支指令可以被编码到仿真代码ROM中，使得与由OpSeq代码控制的分支操作相结合的第二分支被应用于操作代码序列。 双向分支允许灵活分支到仿真代码ROM内的位置，从而节省存储器容量。 超标量微处理器（120）包括具有仿真代码控制电路的指令解码器和模拟逻辑指令解码器的功能的仿真ROM。 仿真码ROM被布置为多操作（Op）单元的矩阵，每个多操作单元包括指向仿真代码ROM中的下一个位置的控制字段。 在一个实施例中，仿真代码ROM被布置成包括称为Op四边形的多个四运算单元，每个Op quad包括称为OpSeq字段的排序控制字段。

公开(公告)号：WO1997010612A1

公开(公告)日：1997-03-20

申请号：PCT/US1996013032

申请日：1996-08-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LIN, Ming-Ren

IPC: H01L21/033

CPC classification number: H01L21/76831 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Submicron contacts/vias and trenches are provided in a dielectric layer by forming an opening having an initial dimension and reducing the initial dimension by depositing a second dielectric material in the opening.

Abstract translation: 通过形成具有初始尺寸的开口并通过在开口中沉积第二介电材料来减小初始尺寸，在介电层中提供亚微米触点/通孔和沟槽。

公开(公告)号：WO1996041456A1

公开(公告)日：1996-12-19

申请号：PCT/US1996004658

申请日：1996-04-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CRAYFORD, Ian

IPC: H04L12/56

CPC classification number: H04L47/10 ,  H04L12/46 ,  H04L47/135 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/40 ,  H04L49/506

Abstract: A flow control enabled Ethernet switch that applies backpressure to input ports that attempt to transmit a data packet to a busy destination port. The backpressure is a phantom packet that activates the IEEE 802.3 collision detection system to abort transmission of the data packet. A subsequent series of phantom packets (that are invalid) provide carrier activity that inhibits retransmission of the packet. When the destination port is available, the phantom packets are stopped, permitting standard retransmission of the data packet. The switch includes prioritization mechanisms (e.g., a throttle count) to use when awarding priority to a port having backpressure applied.

Abstract translation: 启用流量控制的以太网交换机，将反向压力应用于尝试将数据包传输到繁忙目标端口的输入端口。 背压是激活IEEE 802.3冲突检测系统以中止数据分组传输的幻影分组。 随后的一系列虚幻分组（无效）提供禁止分组重传的运营商活动。 当目的端口可用时，幻象分组被停止，允许数据分组的标准重传。 交换机包括在向具有背压的端口授予优先权时使用的优​​先化机制（例如，节气门计数）。

公开(公告)号：WO1996041272A1

公开(公告)日：1996-12-19

申请号：PCT/US1996009757

申请日：1996-06-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GULICK, Dale ,  LAMBRECHT, Andy ,  WEBB, Mike ,  HEWITT, Larry ,  BARNES, Brian

IPC: G06F13/364

CPC classification number: G06F13/364

Abstract: A computer system is provided which includes a bus bridge coupled between a CPU local bus and a PCI bus. The bridge further includes a memory controller for controlling data transfers between a main memory and masters residing on either the CPU local bus or the PCI bus. A variety of peripheral devices are coupled to the PCI bus, including both real time resources and non-real time resources. For example, in one configuration, an SCSI controller, a network interface card, a video adapter, a video capture card, an audio adapter, and a telephony adapter are coupled to the PCI bus. A bus arbiter is advantageously provided for controlling and prioritizing ownership of the PCI bus based in part upon a real time indicator signal asserted by a bus agent that requires a real time data transfer. Each real time device is associated with a unique real time indicator signal. A relatively high level of arbitration priority is given to a master when it asserts its associated real time indicator signal at the time of a bus request. Bus agents which do not assert an associated real time indicator signal at the time of a bus request will lose the arbitration until all real time requests have been serviced. As a result, the system may support numerous real time processing resources while maintaining proper overall operation.

Abstract translation: 提供了一种计算机系统，其包括耦合在CPU本地总线和PCI总线之间的总线桥。 桥接器还包括用于控制主存储器和驻留在CPU本地总线或PCI总线上的主设备之间的数据传输的存储器控​​制器。 各种外围设备耦合到PCI总线，包括实时资源和非实时资源。 例如，在一个配置中，SCSI控制器，网络接口卡，视频适配器，视频采集卡，音频适配器和电话适配器被耦合到PCI总线。 有利地提供总线仲裁器，用于部分地基于由需要实时数据传输的总线代理断言的实时指示符信号来控制和优先化PCI总线的所有权。 每个实时设备与唯一的实时指示符信号相关联。 在总线请求时，当主设备断言其相关联的实时指示符信号时，给予相对较高级别的仲裁优先级。 在总线请求时不断言相关联的实时指示符信号的总线代理将丢失仲裁，直到所有实时请求得到维护为止。 结果，该系统可以支持大量实时处理资源，同时保持适当的整体操作。

公开(公告)号：WO1996039766A1

公开(公告)日：1996-12-12

申请号：PCT/US1996008539

申请日：1996-06-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  STEWART, Brett, B.

IPC: H04L12/28

CPC classification number: H04W36/0072 ,  H04W28/16 ,  H04W76/10 ,  H04W84/12

Abstract: An adjacency matrix is incorporated into a local area network in order to provide smoother and faster transitions between mobile devices and access points of adjacent or overlapping microcells. The adjacency matrix can be based on fuzzy logic and updated periodically. Factors used to create the matrix can include the ability to establish a communication link, signal strength measurements, roam times, time of day, day of week and other factors germane to the local area network topology and patterns of its usage. The mobile device thus effects the transition by attempting to communicate on the frequencies associated with hopping schemes of the access points which are most likely adjacent to the previous access point. As a result, the average transition time is greatly reduced.

Abstract translation: 邻接矩阵被并入到局域网中，以便在移动设备和相邻或重叠的微小区的接入点之间提供更平滑和更快速的转换。 邻接矩阵可以基于模糊逻辑并定期更新。 用于创建矩阵的因素可以包括建立通信链路，信号强度测量，漫游时间，一天中的时间，星期几以及与局域网拓扑和其使用模式密切相关的其他因素的能力。 因此，移动设备通过尝试在最可能与先前接入点相邻的接入点的跳频方案相关联的频率上进行通信来实现转换。 结果，平均过渡时间大大降低。