公开(公告)号：WO1997016830A1

公开(公告)日：1997-05-09

申请号：PCT/US1996012020

申请日：1996-07-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CLEVELAND, Lee, E. ,  CHEN, Johnny, C.

IPC: G11C16/06

CPC classification number: G11C16/3409 ,  G11C16/28 ,  G11C16/3404

Abstract: A reference circuit for overerase correction in a flash memory includes a reference flash memory cell biased in a substantially similar manner to that of an overerased flash memory cell. The leakage current for the reference flash memory cell is preset to a tolerable level of leakage current for a maximum operating temperature of the flash memory and the reference flash memory cell tracks the temperature characteristics of the overerased flash memory cell, to avoid costly overcorrection at high temperatures.

Abstract translation: 用于闪速存储器中过度修正的参考电路包括以基本上类似于过度闪存单元的方式偏置的参考闪存单元。 参考闪存单元的泄漏电流被预设为在闪速存储器的最大工作温度下允许的泄漏电流水平，并且参考闪速存储器单元跟踪过高闪存单元的温度特性，以避免在高处过高的过高校正 温度。

公开(公告)号：WO1997018588A1

公开(公告)日：1997-05-22

申请号：PCT/US1996012122

申请日：1996-07-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CLEVELAND, Lee, E. ,  KIM, Yong, K. ,  CHANG, Chung, K.

IPC: H01L27/02

CPC classification number: H01L27/0222 ,  G11C5/145 ,  H01L27/0629 ,  H01L29/94 ,  H02M3/073

Abstract: A charge pump circuit utilizing accumulation capacitors for use in EEPROM devices so as to internally pump up an external power source voltage includes a plurality of MOS transistors (T101, T102; T201, T202) and accumulation capacitors (N2, P2). The plurality of MOS transistors are connected in series between a first input voltage terminal and a higher voltage output terminal. The first input voltage terminal receives the external power source voltage. The accumulation capacitor has a first plate and a second plate. Each of the first plates of the accumulation capacitors is connected between adjacent ones of the plurality of MOS transistors. Each of the second plates of the accumulation capacitors is connected to a second input terminal for receiving a clock signal. As a result, the pump circuit can be operated effectively so as to produce a significant reduction in power consumption.

Abstract translation: 使用用于EEPROM装置的积累电容器以便内部泵浦外部电源电压的电荷泵电路包括多个MOS晶体管（T101，T102; T201，T202）和累积电容器（N2，P2）。 多个MOS晶体管串联连接在第一输入电压端子和较高电压输出端子之间。 第一输入电压端子接收外部电源电压。 累积电容器具有第一板和第二板。 累积电容器的每个第一板连接在多个MOS晶体管中的相邻元件之间。 累积电容器的每个第二板连接到用于接收时钟信号的第二输入端子。 结果，可以有效地操作泵电路，从而显着降低功耗。

公开(公告)号：WO1997030455A1

公开(公告)日：1997-08-21

申请号：PCT/US1996013232

申请日：1996-08-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHANG, Chung, K. ,  CHEN, Johnny, C. ,  CLEVELAND, Lee, E.

IPC: G11C16/06

CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/073 ,  H02M2003/071 ,  H02M2003/075

Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

Abstract translation: 用于在闪速擦除期间通过闪存EEPROM存储器单元阵列中的字线产生相对高的负电压以控制所选择的存储器单元的栅极的低电源负电荷泵包括由多个电荷泵级形成的电荷泵装置（210） 201-206）和用于将时钟信号传送到多个电荷泵级的耦合电容器装置（C201-C212）。 多个电荷泵级中的每一个由N沟道本征通过晶体管（N1-N6），N沟道本征初始化晶体管（MD1-MD6）和N沟道本征预充电晶体管（MX3-MX7， MX1），其设置在单独的p阱中，以减少身体效应。 结果，负电荷泵可以使用+ 3伏或更低的电源电压工作。

公开(公告)号：WO1996019810A1

公开(公告)日：1996-06-27

申请号：PCT/US1995014220

申请日：1995-11-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  TANG, Yuan ,  CLEVELAND, Lee, E.

IPC: G11C16/06

CPC classification number: G11C16/3477 ,  G11C16/16 ,  G11C16/3468

Abstract: There is provided an improved method for tightening the distribution of control gate threshold voltages of erase cells in flash EEPROM devices. A relatively low positive voltage is applied to the source regions of the EEPROM devices during an entire erase cycle. The magnitude of a negative constant voltage applied to control gates of the EEPROM devices is lowered to a predetermined voltage level during the entire erase cycle so as to obtain a tighter threshold voltage distribution. The value of a load resistor coupled between the low positive voltage and source regions is reduced simultaneously to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage. As a result, an improved threshold voltage VT distribution after erase is obtained without sacrificing any reduction in the erase speed.

Abstract translation: 提供了一种用于紧固闪存EEPROM器件中擦除单元的控制栅极阈值电压分布的改进方法。 在整个擦除周期期间，将相对低的正电压施加到EEPROM器件的源极区域。 施加到EEPROM器件的控制栅极的负的恒定电压的大小在整个擦除周期期间降低到预定的电压电平，以便获得更严格的阈值电压分布。 耦合在低正电压和源极区之间的负载电阻器的值同时减小到预定值，以补偿由负的恒定电压的幅度的降低引起的增加的擦除时间。 结果，在擦除之后获得改善的阈值电压VT分布，而不牺牲擦除速度的任何降低。

公开(公告)号：WO1997019510A1

公开(公告)日：1997-05-29

申请号：PCT/US1996012125

申请日：1996-07-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CLEVELAND, Lee, E.

IPC: H02M03/07

CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/07

Abstract: A voltage booster circuit includes a driver circuit (117) for generating a 3-state output for driving wordlines via row decoder circuits in an array of flash EEPROM memory cells during read and programming modes of operation. The driver circuit effectively disconnects a large booster capacitor (115) in order to allow a small charge pump (114) to further pump up the wordline voltage during programming. As a result, the booster pump has improved efficiency since there is achieved a significant reduction in power consumption.

Abstract translation: 升压电路包括驱动电路（117），用于在读取和编程操作模式期间，通过行闪存EEPROM存储器单元阵列中的行解码器电路产生用于驱动字线的3态输出。 驱动器电路有效地断开大型升压电容器（115），以便在编程期间允许小电荷泵（114）进一步泵送字线电压。 结果，由于实现了功率消耗的显着降低，所以增压泵具有提高的效率。

公开(公告)号：EP0880783B1

公开(公告)日：1999-10-13

申请号：EP96927429.9

申请日：1996-08-15

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CHANG, Chung, K. ,  CHEN, Johnny, C. ,  CLEVELAND, Lee, E.

IPC: G11C16/06 ,  G11C5/14 ,  H02M3/07

CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/073 ,  H02M2003/071 ,  H02M2003/075

Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

公开(公告)号：EP0861517B1

公开(公告)日：1999-10-13

申请号：EP96924686.7

申请日：1996-07-23

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CLEVELAND, Lee, E.

IPC: H02M3/07 ,  G11C5/14

CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/07

公开(公告)号：EP0880783A1

公开(公告)日：1998-12-02

申请号：EP96927429.0

申请日：1996-08-15

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CHANG, Chung, K. ,  CHEN, Johnny, C. ,  CLEVELAND, Lee, E.

IPC: G11C5 ,  G11C16 ,  H02M3

CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/073 ,  H02M2003/071 ,  H02M2003/075

Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

公开(公告)号：EP0858660B1

公开(公告)日：1999-09-15

申请号：EP96924652.9

申请日：1996-07-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CLEVELAND, Lee, E. ,  CHEN, Johnny, C.

IPC: G11C16/06

CPC classification number: G11C16/3409 ,  G11C16/28 ,  G11C16/3404

公开(公告)号：EP0861517A1

公开(公告)日：1998-09-02

申请号：EP96924686.0

申请日：1996-07-23

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CLEVELAND, Lee, E.

IPC: G11C5 ,  G11C16 ,  H02M3

CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/07

Abstract: A voltage booster circuit includes a driver circuit (117) for generating a 3-state output for driving wordlines via row decoder circuits in an array of flash EEPROM memory cells during read and programming modes of operation. The driver circuit effectively disconnects a large booster capacitor (115) in order to allow a small charge pump (114) to further pump up the wordline voltage during programming. As a result, the booster pump has improved efficiency since there is achieved a significant reduction in power consumption.