公开(公告)号：WO1994026525A1

公开(公告)日：1994-11-24

申请号：PCT/US1994005061

申请日：1994-05-04

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  STORTZ, James, L.

IPC: B41J02/205

CPC classification number: B41J2/2128 ,  B41J2202/10

Abstract: A spot size modulatable, drop-on-demand type ink jet printhead (2) for producing grey-scale images on a substrate. The ink jet printhead (2) includes a main body portion (14) having an ink-carrying channel (6) extending therethrough and a piezoelectric actuator (34) coupled to the ink-carrying channel (6). A spot size for droplets to form when striking the substrate after ejection from the ink-carrying channel (6) is selected and a look-up table (54) translates the selected spot size into a time period during which a voltage pulse is to be applied to the piezoelectric actuator (34) by an associated switching structure (62) to initiate application of the voltage waveform, determines whether the voltage waveform has been applied to the piezoelectric actuator (34) for the time period and terminates application of the voltage waveform upon expiration of the time period. The control circuit includes a sequencer (60) which selectively asserts or deasserts at least one control signal to the switching structure, a timer (52) which instructs the sequencer (60) to initiate application of the voltage waveform and determines time elapsed since initiating application, and a comparator (58) which compares the time period produced by the look-up table (54) and the elapsed time determined by the timer (52).

Abstract translation: 用于在基板上产生灰度图像的点尺寸可调节按需喷墨打印头（2）。 喷墨打印头（2）包括具有延伸穿过其中的墨水输送通道（6）的主体部分（14）和耦合到墨水输送通道（6）的压电致动器（34）。 选择在从墨水输送通道（6）喷射之后撞击基板时形成的液滴的光斑尺寸，并且查找表（54）将所选择的光点尺寸转换为电压脉冲将在该时间段内 通过相关联的开关结构（62）施加到压电致动器（34）以开始施加电压波形，确定电压波形是否已经施加到压电致动器（34）一段时间并终止施加电压波形 期限届满时。 所述控制电路包括定序器（60），其选择性地向所述开关结构断言或解除至少一个控制信号;定时器（52），其指示所述定序器（60）开始施加所述电压波形并确定自启动应用以来经过的时间 ，以及比较器（58），其比较由查找表（54）产生的时间周期和由定时器（52）确定的经过时间。

公开(公告)号：WO1994016379A1

公开(公告)日：1994-07-21

申请号：PCT/US1994000333

申请日：1994-01-11

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  WALKER, Richard, E.

IPC: G06F01/32

CPC classification number: G06F1/3218 ,  G09G2330/021

Abstract: A computer system has a monitor which can be powered down to conserve electrical power. The monitor has two power modes, normal power mode and low power mode. Upon receiving a signal from the CPU, the monitor switches betwen power modes.

Abstract translation: 计算机系统具有可以断电以节省电力的监视器。 显示器有两种电源模式，正常电源模式和低功耗模式。 监视器从CPU接收到信号后，会在电源模式之间切换。

公开(公告)号：WO1994008445A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009203

申请日：1993-09-24

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  GEBARA, Ghassan, R.

IPC: H05K09/00

CPC classification number: H05K1/0218 ,  H05K1/0219 ,  H05K9/0039 ,  H05K2201/093

Abstract: An EMR reduction technique using grounded conductive traces and vias circumscribing the internal planes of printed wiring boards. Conductive vias are placed in a circuitous path near the border and encircling the signal traces of each layer of a printed circuit board. The ground plane is extended to encompass and electrically ground each of the vias. For each signal plane, a conductive trace is routed and connected to each of the vias forming a grounded shield around the signal-carrying traces on the signal plane. For the power planes, a conductive trace is also provided connecting the conductive vias and forming a grounded shield around the power planes. A non-conductive path is provided between the power plane and the power plane conductive trace to electrically isolate the voltages of the power plane from the grounded conductive trace.

Abstract translation: 使用接地导电迹线和通孔限制印刷电路板的内部平面的EMR降低技术。 导电通孔放置在靠近边界的迂回路径中并且环绕印刷电路板的各层的信号迹线。 接地平面被延伸以包围和电接地每个通孔。 对于每个信号平面，导电迹线被路由并连接到在信号平面上的信号载体迹线周围形成接地屏蔽的每个通孔。 对于电源平面，还提供连接导电通孔并在电源平面周围形成接地屏蔽的导电迹线。 在电源平面和电源平面导电迹线之间提供非导电路径，以将电源平面的电压与接地的导电迹线电隔离。

公开(公告)号：WO1994008313A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009410

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  CULLEY, Paul, R. ,  LANDRY, John, A. ,  MAYER, Dale, J. ,  WANNER, Christopher, C. ,  McSWAIN, Guy, E.

IPC: G06F15/80

CPC classification number: G06F15/8015 ,  G06F13/24 ,  G06F13/32

Abstract: An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.

Abstract translation: 在多处理器计算机系统中安排直接存储器访问（DMA），中断和定时器功能，以允许对称处理。 被认为是所有CPU通用的几个功能以及通过扩展总线方便地访问的那些功能保留在耦合到扩展总线的中央系统外围芯片中。 这些中心功能包括DMA控制器的主要部分和控制扩展总线访问的仲裁电路。 本地为每个CPU提供了分布式外设，包括可编程中断控制器，多处理器中断逻辑，不可屏蔽中断逻辑，本地DMA逻辑和定时器功能。 在中央和分布式外设之间提供总线，以允许中央外设向CPU广播信息，并且当本地CPU在中央外设中编程或访问功能时，将分布式芯片的本地信息提供给中央外设。

公开(公告)号：WO1994008302A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009362

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  MELO, Maria, L. ,  WOLFORD, Jeff, W. ,  MORIARTY, Michael ,  CULLEY, Paul, R. ,  SCHNELL, Arnold, T.

IPC: G06F13/36

CPC classification number: G06F13/36 ,  G06F13/362

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Abstract translation: 用于确定多个CPU中的哪一个接收优先权以成为多处理器系统中的主机总线的总线的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制何时发生，由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 拆分事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被其他设备控制，数据在空闲时也在主机总线上被断言。

公开(公告)号：WO1994008301A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009186

申请日：1993-09-24

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  TIPLEY, Roger, E. ,  MORIARTY, Michael ,  TAYLOR, Mark

IPC: G06F13/36

CPC classification number: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Abstract translation: 用于确定多个CPU中的哪一个接收优先权以成为多处理器系统中的主机总线的总线的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制何时发生，由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 拆分事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被其他设备控制，数据在空闲时也在主机总线上被断言。

公开(公告)号：WO1994008300A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009411

申请日：1993-09-30

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  MAYER, Dale, J. ,  LANDRY, John, A. ,  CULLEY, Paul, R.

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: A method and apparatus which maintains strict ordering of processor cycles to guarantee that a processor write, such as an EOI instruction, is not executed to the interrupt controller prior to the interrupt request from a requesting device being cleared at the interrupt controller, thus maintaining system integrity. Interrupt controller logic is included on each respective CPU board. The processor can access the interrupt controller over a local bus without having to access the host bus or the expansion bus and thus an interrupt controller access could be completed before a previously generated I/O cycle has completed. Therefore, the apparatus which tracks expansion bus cycles and interrupt controller accesses and maintains strict ordering of these cycles to guarantee that an interrupt request is cleared at the interrupt controller prior to execution of write operation to the interrupt controller.

Abstract translation: 一种保持处理器周期的严格排序以保证在来自请求设备在中断控制器处被清除的中断请求之前不向中断控制器执行诸如EOI指令之类的处理器写入的方法和装置，因此维护系统 完整性。 中断控制器逻辑包含在每个相应的CPU板上。 处理器可以通过本地总线访问中断控制器，而无需访问主机总线或扩展总线，因此在先前生成的I / O周期完成之前可以完成中断控制器访问。 因此，跟踪扩展总线周期和中断控制器的设备访问并维护这些周期的严格排序，以保证在执行到中断控制器的写操作之前在中断控制器处清除中断请求。

公开(公告)号：WO1994008298A2

公开(公告)日：1994-04-14

申请号：PCT/US1993009363

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  GALLOWAY, William, C.

IPC: G06F13/12

CPC classification number: G06F13/126

Abstract: A method for improving SCSI controller operations by actively patching SCSI processor instructions. In a first case, tag values assigned to queues for tagged queue operation are a multiple of the SCSI processor jump instruction length. When reselected, the tag value is patched or overwritten as the least significant byte of the address of a jump instruction. The upper bytes point to the beginning of a jump table. Each entry in the jump table is a jump instruction to the sequence for a particular queue or thread. Thus simple entry is made to the desired thread without a conditional branch tree. In a second case, special SCSI operations are directly handled by the host device driver and the SCSI processor only performs conventional data transfers and similar operations. The device driver patches the message length of the SCSI processor code to an illegal value, so that an illegal instruction develops, prompting the host device driver to perform the operation at a register level. This approach allows removal of all special operation conditional branching from the SCSI processor, greatly speeding up operations.

Abstract translation: 通过主动修补SCSI处理器指令来改进SCSI控制器操作的方法。 在第一种情况下，分配给用于标记队列操作的队列的标签值是SCSI处理器跳转指令长度的倍数。 当重新选择时，标签值被修补或重写为跳转指令的地址的最低有效字节。 高字节指向跳转表的开头。 跳转表中的每个条目是针对特定队列或线程的序列的跳转指令。 因此，在没有条件分支树的情况下，对所需的线程进行简单的输入。 在第二种情况下，专用SCSI操作由主机设备驱动程序直接处理，SCSI处理器仅执行常规数据传输和类似操作。 设备驱动程序将SCSI处理器代码的消息长度修补为非法值，从而开发非法指令，提示主机设备驱动程序在注册级执行操作。 这种方法允许从SCSI处理器中删除所有特殊操作条件分支，大大加快了操作。

公开(公告)号：WO1994008296A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009366

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  CULLEY, Paul, R. ,  TAYLOR, Mark

IPC: G06F12/02

CPC classification number: G06F13/1673 ,  G06F12/0215 ,  G06F13/4018

Abstract: Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system data buffer coupled between the main memory and the expansion bus includes 256-bit double read and write buffers. A memory controller coupled to the double read and write buffers and to the expansion bus includes primary and secondary address latches corresponding to the double buffers. The memory controller detects access to the main memory, compares the expansion bus address with the primary and secondary addresses and controls the double read and write buffers and the primary and secondary address latches accordingly. During write operations, data to be written to the same line of memory is written to a first of the double write buffers until a write occurs to an address to a different line before data is transferred to main memory. During read operations, a full line is loaded into a first of the double read buffers, and the next full line is retrieved into a second read buffer from main memory if a subsequent read hit occurs in the first read buffer.

Abstract translation: 双缓存操作，以减少扩展总线主机访问计算机系统的主机总线上的主存储器时的主机总线保持时间。 耦合在主存储器和扩展总线之间的系统数据缓冲器包括256位双重读写缓冲器。 耦合到双读和写缓冲器和扩展总线的存储器控​​制器包括对应于双缓冲器的主地址和副地址锁存器。 存储器控制器检测对主存储器的访问，将扩展总线地址与主地址和辅助地址进行比较，并相应地控制双读和写缓冲器以及主地址和副地址锁存器。 在写入操作期间，要写入同一行存储器的数据被写入双写缓冲器中的第一个，直到在将数据传送到主存储器之前写入到不同行的写入。 在读取操作期间，如果在第一个读取缓冲器中发生后续读取命中，则将全行加载到第一个双重读取缓冲区中，并且将下一个完整行从主存储器检索到第二个读取缓冲区中。

公开(公告)号：WO1994008291A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009365

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  LANDRY, John, A.

IPC: G06F15/16

CPC classification number: G06F11/1417 ,  G06F9/4405 ,  G06F11/0724 ,  G06F11/0757 ,  G06F11/22 ,  G06F15/177

Abstract: A multiprocessor computer system includes fault tolerant power up logic for finding a functioning CPU to operate as logical CPU0. Each microprocessor has a physical location designation which remains constant. When the system is powered up, all of the CPUs except the CPU in physical slot 0 (CPU P0) are initially placed in an inactive sleep state. The microprocessor in physical location 0 performs its power on self test (POST), and if the CPU functions properly, the CPU is designated as logical CPU0 (CPU L0). The microprocessor then awakens the remaining CPUs and boots up the rest of the computer system. If CPU P0 is not functioning properly, after a given time period the system awakens the processor in the next physical location and repeats the process of testing the CPU. The process repeats until an operating microprocessor is found to perform the CPU L0 functions.

Abstract translation: 多处理器计算机系统包括用于寻找作为逻辑CPU0操作的功能CPU的容错上电逻辑。 每个微处理器具有保持恒定的物理位置指定。 当系统通电时，物理槽0（CPU P0）以外的CPU中的所有CPU都处于非活动状态。 物理位置0的微处理器执行自检电源（POST），如果CPU正常工作，CPU被指定为逻辑CPU0（CPU L0）。 然后微处理器唤醒剩余的CPU并启动计算机系统的其余部分。 如果CPU P0无法正常工作，在给定的时间段内，系统会在下一个物理位置唤醒处理器，并重复测试CP​​U的过程。 该过程重复，直到发现操作微处理器执行CPU L0功能。