公开(公告)号：GB2488259A

公开(公告)日：2012-08-22

申请号：GB201207123

申请日：2010-12-09

Applicant: IBM

Inventor： ELEFTHERIOU EVANGELOS S ,  HAAS ROBERT ,  HU XIAO-YU

IPC: G06F13/16

Abstract: A Flash memory controller is coupled to a first Flash memory package through a first Flash memory interface and to a second Flash memory package through the first Flash memory interface. The Flash memory controller is designed to receive a first instruction relating to the first Flash memory package and to perform a first process depending on the first instruction. The Flash memory controller is further designed to receive a second instruction relating to the second Flash memory package and to perform a second process depending on the second instruction. The Flash memory controller is further adapted for splitting the first process into at least two first sub-steps and for splitting the second process into at least two second sub-steps. The Flash memory controller is further adapted for executing the first and second sub-steps, and for interleaving execution of first and second sub-steps.

公开(公告)号：MX2012007899A

公开(公告)日：2012-08-01

申请号：MX2012007899

申请日：2011-05-25

Applicant: IBM

Inventor： ELEFTHERIOU EVANGELOS S ,  HAAS ROBERT ,  HU XIAOYU ,  NGUYEN DUNG VIET

IPC: H03M13/11

Abstract: Se proporciona un método para la decodificación de una secuencia de bits codificada por un código LPDC. El método comprende proporcionar un conjunto de estados de los bits, incluyendo un primer estado y un segundo estado, y un conjunto de condiciones para cambiar un estado del bit que incluye una primera condición y una segunda condición. La primera condición y la segunda condición son diferentes. El método comprende leer el valor de cada bit de la secuencia, asociar cada bit a un estado respectivo del conjunto, de acuerdo con los valores como se leen, determinar que una condición evaluada se cumple y cambiar el estado del bit objetivo como resultado de que la condición se cumpla. El método puede fijar entonces el valor del bit objetivo de la secuencia de acuerdo con el estado del mismo. Tal método proporciona una solución para la decodificación de una secuencia de bits codificada por un código LDPC con mejor desempeño que el algoritmo de inversión de los bits clásico, sólo con un ligero incremento en la complejidad.

公开(公告)号：DE60300999T2

公开(公告)日：2006-04-20

申请号：DE60300999

申请日：2003-04-16

Applicant: IBM

Inventor： ANTONAKOPOULOS THEODOROS ,  BINNIG GERD K ,  ELEFTHERIOU EVANGELOS S

IPC: G11B20/10 ,  G11B9/00 ,  H03M5/04

公开(公告)号：AU2003224007A1

公开(公告)日：2003-10-08

申请号：AU2003224007

申请日：2003-03-10

Applicant: IBM

Inventor： ELEFTHERIOU EVANGELOS S ,  OELCER SEDAT ,  ABDELILAH YOUSSEF ,  DAVIS GORDON TAYLOR ,  DERBY JEFF H ,  HWANG DONGMING ,  WARE MALCOLM ,  YE HUA

IPC: H04L29/06 ,  H04M11/06 ,  H04Q11/00

Abstract: A method and systems for optimizing Asymmetric Digital Subscriber Line (ADSL) connections in DSL Access Multiplexor (DSLAM) that marries benefits of G.dmt and G.lite standards, using a flexible method implemented on a programmable Digital Signal Processor (DSP) and a Network Processor (NP) is disclosed. It provides a means to support full G.dmt rates for any of the attached users as long as less than half the users are actively moving data through the DSLAM, but by only using half the digital signal processing hardware and half the power consumption for the line drivers. The invention allows doubling the number of,ADSL ports available over a conventional scheme given about 20% more power is under 50% with only half the respective connections, all those G.dmt rates possible on their exceeds 50%, gradually active G.lite rates based on either based on a tiered tariff structure, until ultimately, when the utilization reaches 100%, all subscribers will be forced back to a maximum rate afforded by G.lite. Only as utilization drops back off, will active subscribers be brought back up to G.dmt's maximum transmission rates. Once the utilization drops below 50% again, then all active subscribers will be able to utilize G.dmt's maximum transmission rates. budget. When the utilization subscribers active on their users experience the maximum wire. However, when utilization subscribers start to experience a fixed policy or one that is based on a tiered tariff structure, until ultimately, when the utilization reaches 100%, all subscribers will be forced back to a maximum rate afforded by G.lite. Only as utilization drops back off, will active subscribers be brought back up to G.dmt's maximum transmission rates. Once the utilization drops below 50% again, then all active subscribers will be able to utilize G.dmt's maximum transmission rates.

公开(公告)号：HU0103435A2

公开(公告)日：2002-01-28

申请号：HU0103435

申请日：1999-08-31

Applicant: IBM

Inventor： BUSH GREGORY S ,  CIDECIYAN ROY D ,  COKER JONATHAN D ,  ELEFTHERIOU EVANGELOS S ,  GALBRAITH RICHARD L ,  STANEK DAVID J

IPC: G06F11/08 ,  G06F11/10 ,  G11B20/10 ,  G11B20/18 ,  G11B20/22 ,  H03M13/00 ,  H03M13/39 ,  H04L25/03 ,  H04L25/497

Abstract: A noise-predictive data detection method and apparatus are provided for enhanced noise-predictive maximum-likelihood (NPML) data detection in a direct access storage device. A data signal from a data channel in the direct access storage device is applied to a maximum-likelihood detector that provides an estimated sequence signal. A noise bleacher filter having a frequency response of (1+ alpha D)/1- beta D2) receives a combined estimated sequence signal and data signal and provides a noise filtered signal. A matching and error event filter receives the noise filtered signal and provides an error event filtered signal. An error correction unit receives the estimated sequence signal from the maximum-likelihood detector and receives the error event filtered signal and provides an error corrected estimated sequence signal.