公开(公告)号：JP2003115768A

公开(公告)日：2003-04-18

申请号：JP2002199657

申请日：2002-07-09

Applicant: IBM

Inventor： ELEFTHERIOU EVANGELOS STAVROS ,  GALBRAITH RICHARD L ,  OELCER SEDAT

IPC: H03M13/19 ,  G11B20/18 ,  H03M13/09 ,  H03M13/11 ,  H03M13/29 ,  H04L1/00

Abstract: PROBLEM TO BE SOLVED: To provide a parity check matrix connected to an LDPC code having the encoding complexity of a linear time. SOLUTION: This data low density parity check (LDPC) encoding method comprises a step for defining a first M×N parity check matrix, a step for generating a second parity check matrix having M×M triangle part matrix based on the first parity check matrix, and a step for mapping the data to the LDPC code word based on the second parity check matrix. This method is made valid especially for a data communication application, and also may be used for another application such as a data storage.

公开(公告)号：JPH1125602A

公开(公告)日：1999-01-29

申请号：JP13358298

申请日：1998-05-15

Applicant: IBM

Inventor： COKER JONATHAN D ,  EVANGEROS S EREFUMORIU ,  GALBRAITH RICHARD L ,  WALTER HIRTH

IPC: G11B5/00 ,  G11B5/012 ,  G11B20/10 ,  H03M7/00 ,  H03M13/23 ,  H04L25/03 ,  H03M13/12

Abstract: PROBLEM TO BE SOLVED: To provide a method and device for detecting the data of a partial response maximum liklihood (PRML) data channel in a direct access storage device. SOLUTION: A class IV partial response (PR4) signal is applied to a PR4 viterbi detector 60, and a PR4 viterbi output is generated, and is applied to a first matching delay circuit 64, and a delay PR4 signal is generated. The PR4 viterbi output is subtracted from the delay PR4 signal, and a synthetic signal is applied to a first filter 74 having a frequency response 1/ (1-αD ). A filtered output signal is applied to a second filter 76, and a second filter output signal is generated. The PR4 viterbi output is applied to a second matching delay circuit 86, and a delay PR4 viterbi output signal is generated. The delay PR4 viterbi output is responded to the second filter output signal to be corrected. The first filter is an infinite impulse response (IIR) filter, and the filter output signal shows a white colored noise and a corrected PRML error event.

公开(公告)号：GB2355165B

公开(公告)日：2003-10-22

申请号：GB0016683

申请日：2000-07-07

Applicant: IBM

Inventor： CIDECIYAN ROY D ,  COKER JONATHAN D ,  ELEFTHERIOU EVANGELOS ,  GALBRAITH RICHARD L ,  TRUAX TODD

IPC: G11B20/14 ,  G11B20/18 ,  H03M5/14 ,  G06F11/10 ,  H03M7/14 ,  H03M7/42 ,  H03M13/01 ,  H03M13/05 ,  H03M13/31 ,  H04L1/00 ,  H04L25/49

Abstract: A method and apparatus for encoding a plurality of successive m-bit binary data words to produce a plurality of successive of n-bit binary code words, where n and m are positive integers and n is greater than m, for supply to a magnetic recording channel. Each m-bit binary data word is partitioned into a plurality of blocks of bits, and at least one said blocks of bits in each m-bit binary data word is encoded in accordance with a finite-state coding scheme to produce a plurality of successive n-bit binary code words. At least one stage of violation correction which transforms the plurality of successive n-bit binary code words. Violation correction includes detecting the occurrence of any of a plurality of prohibited bit patterns at one or more predetermined locations within each n-bit binary coded word, and replacing any prohibited bit pattern so detected by a corresponding substitute bit pattern. The finite-state coding scheme, the prohibited bit patterns, and corresponding substitute bit patterns are predetermined such that in a serial bit-steam comprising the successive n-bit binary code words, the maximum number of consecutive bits of a first value is limited to a first predetermined number j, where b greater or equal to 2, and the maximum number of consecutive bits of the a second value is limited to a second predetermined number k.

公开(公告)号：HU0103435A2

公开(公告)日：2002-01-28

申请号：HU0103435

申请日：1999-08-31

Applicant: IBM

Inventor： BUSH GREGORY S ,  CIDECIYAN ROY D ,  COKER JONATHAN D ,  ELEFTHERIOU EVANGELOS S ,  GALBRAITH RICHARD L ,  STANEK DAVID J

IPC: G06F11/08 ,  G06F11/10 ,  G11B20/10 ,  G11B20/18 ,  G11B20/22 ,  H03M13/00 ,  H03M13/39 ,  H04L25/03 ,  H04L25/497

Abstract: A noise-predictive data detection method and apparatus are provided for enhanced noise-predictive maximum-likelihood (NPML) data detection in a direct access storage device. A data signal from a data channel in the direct access storage device is applied to a maximum-likelihood detector that provides an estimated sequence signal. A noise bleacher filter having a frequency response of (1+ alpha D)/1- beta D2) receives a combined estimated sequence signal and data signal and provides a noise filtered signal. A matching and error event filter receives the noise filtered signal and provides an error event filtered signal. An error correction unit receives the estimated sequence signal from the maximum-likelihood detector and receives the error event filtered signal and provides an error corrected estimated sequence signal.

公开(公告)号：GB2355165A

公开(公告)日：2001-04-11

申请号：GB0016683

申请日：2000-07-07

Applicant: IBM

Inventor： CIDECIYAN ROY D ,  COKER JONATHAN D ,  ELEFTHERIOU EVANGELOS ,  GALBRAITH RICHARD L ,  TRUAX TODD

IPC: G11B20/14 ,  G11B20/18 ,  H03M5/14 ,  G06F11/10 ,  H03M7/14 ,  H03M7/42 ,  H03M13/01 ,  H03M13/05 ,  H03M13/31 ,  H04L1/00 ,  H04L25/49

Abstract: Methods and apparatus are provided for encoding a succession of m-bit data words to produce a succession of n-bit code words, where n > m, for supply to a magnetic recording channel. Each m-bit data word is partitioned into a plurality of blocks of bits (5a, 6a, 7a), and at least one of said blocks is encoded (5, 6, 7) in accordance with a block coding scheme such that the resulting bit sequence derived from the m bits of the data word comprises an n-bit sequence (5b, 6b, 7b). An n-bit code word is then produced by at least one stage of violation correction (8,9). The or each stage of violation correction comprises detecting the occurrence of any of a plurality of prohibited bit patterns at one or more predetermined locations in the n-bit sequence, and replacing any prohibited bit pattern so detected by a respective substitute bit pattern (8b, 9b). The block coding scheme and the prohibited and substitute bit patterns are predetermined such that, in a succession of said n-bit code words, the maximum number of consecutive bits of one value is limited to a first predetermined number j, where j / 2, and the maximum number of consecutive bits of the other value is limited to a second predetermined number k.