公开(公告)号：WO2007051693A3

公开(公告)日：2007-06-28

申请号：PCT/EP2006067340

申请日：2006-10-12

Applicant: IBM ,  IBM UK ,  HUTCHINS ROBERT ALLEN ,  ELEFTHERIOU EVANGELOS ,  OELCER SEDAT ,  JELITTO JENS

Inventor： HUTCHINS ROBERT ALLEN ,  ELEFTHERIOU EVANGELOS ,  OELCER SEDAT ,  JELITTO JENS

IPC: G11B20/10 ,  H03H21/00 ,  H04L25/03

CPC classification number: G11B20/10009 ,  G11B20/10046 ,  G11B20/10175 ,  G11B20/10481 ,  H04L25/03019 ,  H04L2025/03484 ,  H04L2025/03681

Abstract: An apparatus, system, and method are disclosed for adaptive asynchronous equalization using leakage. An equalizer sums products of a plurality of tap signals from a delay line sampling a read signal and a plurality of corresponding tap coefficients to form an equalized signal in an asynchronous time domain having a first sampling rate. A leaky function module calculates a leaky function for each tap coefficient in the asynchronous time domain. An adaptation module adapts each of the tap coefficients as the leaky function for each tap coefficient summed with a signal-dependent updating function for each tap coefficient.

Abstract translation: 公开了一种使用泄漏进行自适应异步均衡的装置，系统和方法。 均衡器对来自对读取信号进行采样的延迟线和多个对应抽头系数的多个抽头信号的乘积进行求和，以在具有第一采样率的异步时域中形成均衡的信号。 泄漏功能模块计算异步时域中每个抽头系数的泄漏函数。 适配模块将每个抽头系数适配为每个抽头系数的泄漏函数，用于针对每个抽头系数的与信号相关的更新函数相加。

公开(公告)号：WO03081942A8

公开(公告)日：2004-09-10

申请号：PCT/EP0303248

申请日：2003-03-10

Applicant: IBM ,  IBM FRANCE ,  ELEFTHERIOU EVANGELOS S ,  OELCER SEDAT ,  ABDELILAH YOUSSEF ,  DAVIS GORDON TAYLOR ,  DERBY JEFF H ,  HWANG DONGMING ,  WARE MALCOLM ,  YE HUA

Inventor： ELEFTHERIOU EVANGELOS S ,  OELCER SEDAT ,  ABDELILAH YOUSSEF ,  DAVIS GORDON TAYLOR ,  DERBY JEFF H ,  HWANG DONGMING ,  WARE MALCOLM ,  YE HUA

IPC: H04L29/06 ,  H04M11/06 ,  H04Q11/00

CPC classification number: H04Q11/00 ,  H04M11/062 ,  H04Q2213/13003 ,  H04Q2213/13039 ,  H04Q2213/1308 ,  H04Q2213/13099 ,  H04Q2213/13199 ,  H04Q2213/13332

Abstract: A method and systems for optimizing Asymmetric Digital Subscriber Line (ADSL) connections in DSL Access Multiplexor (DSLAM) that marries benefits of G.dmt and G.lite standards, using a flexible method implemented on a programmable Digital Signal Processor (DSP) and a Network Processor (NP) is disclosed. It provides a means to support full G.dmt rates for any of the attached users as long as less than half the users are actively moving data through the DSLAM, but by only using half the digital signal processing hardware and half the power consumption for the line drivers. The invention allows doubling the number of,ADSL ports available over a conventional scheme given about 20% more power is under 50% with only half the respective connections, all those G.dmt rates possible on their exceeds 50%, gradually active G.lite rates based on either based on a tiered tariff structure, until ultimately, when the utilization reaches 100%, all subscribers will be forced back to a maximum rate afforded by G.lite. Only as utilization drops back off, will active subscribers be brought back up to G.dmt's maximum transmission rates. Once the utilization drops below 50% again, then all active subscribers will be able to utilize G.dmt's maximum transmission rates. budget. When the utilization subscribers active on their users experience the maximum wire. However, when utilization subscribers start to experience a fixed policy or one that is based on a tiered tariff structure, until ultimately, when the utilization reaches 100%, all subscribers will be forced back to a maximum rate afforded by G.lite. Only as utilization drops back off, will active subscribers be brought back up to G.dmt's maximum transmission rates. Once the utilization drops below 50% again, then all active subscribers will be able to utilize G.dmt's maximum transmission rates.

Abstract translation: 一种用于优化DSL访问多路复用器（DSLAM）中的非对称数字用户线路（ADSL）连接的方法和系统，其使用G.dmt和G.lite标准的优点，使用在可编程数字信号处理器（DSP）和 网络处理器（NP）被公开。 只要不到一半的用户通过DSLAM主动移动数据，但只能使用一半的数字信号处理硬件和一半的功耗来提供支持所有连接用户的全部G.dmt速率的方法 线路驱动程序。 本发明允许将常规方案的ADSL端口数量增加一倍，因为大约20％的功率在50％以下，而仅有一半的相应连接，所有这些G.dmt速率可能超过50％，逐渐活跃的G.lite 价格基于分层关税结构，直到最终使用率达到100％时，所有用户将被迫恢复到由G.lite提供的最高价格。 只有在利用率下降的情况下，活跃用户才能恢复到G.dmt的最大传输速率。 一旦使用率再次下降到50％以下，那么所有活跃用户将能够利用G.dmt的最大传输速率。 预算。 当用户在其用户上活跃时，体验到最大的线路。 然而，当利用者开始体验固定的政策或基于分级关税结构的政策时，直到最终使用率达到100％时，所有用户将被迫恢复到由G.lite提供的最高利率。 只有在利用率下降的情况下，活跃用户才能恢复到G.dmt的最大传输速率。 一旦使用率再次下降到50％以下，那么所有活跃用户将能够利用G.dmt的最大传输速率。

公开(公告)号：JP2003115768A

公开(公告)日：2003-04-18

申请号：JP2002199657

申请日：2002-07-09

Applicant: IBM

Inventor： ELEFTHERIOU EVANGELOS STAVROS ,  GALBRAITH RICHARD L ,  OELCER SEDAT

IPC: H03M13/19 ,  G11B20/18 ,  H03M13/09 ,  H03M13/11 ,  H03M13/29 ,  H04L1/00

Abstract: PROBLEM TO BE SOLVED: To provide a parity check matrix connected to an LDPC code having the encoding complexity of a linear time. SOLUTION: This data low density parity check (LDPC) encoding method comprises a step for defining a first M×N parity check matrix, a step for generating a second parity check matrix having M×M triangle part matrix based on the first parity check matrix, and a step for mapping the data to the LDPC code word based on the second parity check matrix. This method is made valid especially for a data communication application, and also may be used for another application such as a data storage.

公开(公告)号：JP2009095027A

公开(公告)日：2009-04-30

申请号：JP2008262279

申请日：2008-10-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HUTCHINS ROBERT ALLEN ,  JELITTO JENS ,  OELCER SEDAT

IPC: H03L7/08 ,  G11B20/14 ,  G11B20/18 ,  H03L7/06

Abstract: PROBLEM TO BE SOLVED: To provide frequency error combination logic for a multi-channel data detection system with a phase locked loop for each channel.
SOLUTION: The frequency error combination logic comprises receiving frequency error information with respect to each channel; combination logic configured to combine the received frequency error information and generate a combined phase error, weighting the received frequency error information from each channel; and a frequency error output configured to apply the combined frequency error to at least one channel phase locked loop.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为具有每个通道的锁相环的多通道数据检测系统提供频率误差组合逻辑。 解决方案：频率误差组合逻辑包括相对于每个通道接收频率误差信息; 组合逻辑，其被配置为组合所接收的频率误差信息并产生组合的相位误差，从每个信道对所接收的频率误差信息进行加权; 以及频率误差输出，被配置为将组合的频率误差应用于至少一个通道锁相环。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2002344658A

公开(公告)日：2002-11-29

申请号：JP2002078556

申请日：2002-03-20

Applicant: IBM

Inventor： DAVIS GORDON TAYLOR ,  DERBY JEFFREY HASKELL ,  ELEFTHERIOU EVANGELOS STAVROS ,  OELCER SEDAT ,  WARE MALCOLM SCOTT

IPC: H04Q3/42 ,  H04L5/02 ,  H04L5/14 ,  H04M11/00

Abstract: PROBLEM TO BE SOLVED: To substantially reduce the overall power requirement of a line driver connected to a digital subscriber line DSL by limiting a bandwidth of a signal transmitted to all subscriber lines other than those connected to an intended recipient of a physical data frame. SOLUTION: A shared digital subscriber line modem achieves reduced total power consumption and aquires data security by generating and transmitting a physical data frame which includes a control channel and a data field to only the connected client modem associated with the intended recipient. A second physical frame which does not include the data field is generated and transmitted to all of the other connected client modems.

公开(公告)号：JP2006313615A

公开(公告)日：2006-11-16

申请号：JP2006122711

申请日：2006-04-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HUTCHINS ROBERT A ,  ELEFTHERIOU EVANGELOS S ,  OELCER SEDAT

IPC: G11B20/10 ,  G11B20/14

CPC classification number: G11B20/10 ,  G11B20/10009 ,  G11B20/10046

Abstract: PROBLEM TO BE SOLVED: To efficiently identify a channel dibit response based on a DSS sequence. SOLUTION: A dibit response estimation generator receives a DSS sequence and a DSS read-back sequence, which is a function of channel processing of the DSS sequence by a read channel. The generator generates a cyclic dibit response vector as the functions of the DSS sequence and DSS read-back sequence. Further, the generator generates an error signal as the function of comparison of the DSS read-back sequence and filtering of the DSS sequence based on the cyclic dibit response vector. An unacceptable error signal indicates a need to adjust the cyclic dibit response vector so as to yield acceptable comparison of the DSS read-back sequence with the filtering of the DSS sequence based on the cyclic dibit response vector. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了有效地识别基于DSS序列的信道双向响应。 解决方案：双向响应估计生成器接收DSS序列和DSS回读序列，DSS序列是读通道对DSS序列的通道处理的函数。 发生器生成循环双位响应向量作为DSS序列和DSS回读序列的功能。 此外，发生器产生作为DSS回读序列的比较和基于循环双位响应向量的DSS序列的滤波的函数的误差信号。 不可接受的误差信号表示需要调整循环双位响应向量，以便基于循环双位响应向量产生DSS回读序列与DSS序列的过滤的可接受的比较。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006221783A

公开(公告)日：2006-08-24

申请号：JP2006019666

申请日：2006-01-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BERMAN DAVID ,  ELEFTHERIOU EVANGELOS S ,  HUTCHINS ROBERT ALLEN ,  JAQUETTE GLEN ALAN ,  MELAS CONSTANTIN M ,  OELCER SEDAT

IPC: G11B20/14 ,  G11B20/10 ,  G11B20/18 ,  H03M13/41

CPC classification number: G11B20/10009 ,  G11B20/10046 ,  G11B20/10296 ,  G11B2220/2516

Abstract: PROBLEM TO BE SOLVED: To provide a device, a system, and a method for detecting asymmetrical maximum likelihood.
SOLUTION: In an initialization module, a plurality of branch metrics and a plurality of path memories are initialized. In a coefficient module, a plurality of coefficients are calculated. In the calculation module, a first and second designated likelihood functions are calculated. In a selection module, a third designated branch metric is calculated as the maximum value among the first and the second designated likelihood functions. In the path metric module, the third designated path memory is calculated from a first and second designated path memory. In a result module, a data output value is identified from one or more path memories.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于检测不对称最大似然性的装置，系统和方法。 解决方案：在初始化模块中，初始化多个分支度量和多个路径存储器。 在系数模块中，计算多个系数。 在计算模块中，计算第一和第二指定似然函数。 在选择模块中，第三指定分支度量被计算为第一和第二指定似然函数中的最大值。 在路径度量模块中，从第一和第二指定路径存储器计算第三指定路径存储器。 在结果模块中，从一个或多个路径存储器识别数据输出值。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2009095028A

公开(公告)日：2009-04-30

申请号：JP2008262296

申请日：2008-10-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HUTCHINS ROBERT ALLEN ,  JELITTO JENS ,  OELCER SEDAT

IPC: H03L7/091

Abstract: PROBLEM TO BE SOLVED: To provide phase-error combination logic for a multi-channel data detection system with a phase locked loop for each channel.
SOLUTION: The phase-error combination logic comprises receiving phase error information with respect to each channel; combination logic configured to combine the received phase error information and generate a combined phase error; and a phase-error output configured to apply the combined phase error to at least one channel phase locked loop. Additionally, error signal combination logic comprises receiving error information of a signal relevant to a phase locked loop with respect to each channel; combination logic configured to combine the received error signal information and generate a combined error signal, weighting the received error signal information from each channel, for example with reliability information. An error compensation output is configured to apply the combined, weighted error signal to at least one channel phase locked loop.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为具有每个通道的锁相环的多通道数据检测系统提供相位误差组合逻辑。 解决方案：相位误差组合逻辑包括接收关于每个通道的相位误差信息; 组合逻辑，被配置为组合所接收的相位误差信息并产生组合的相位误差; 以及被配置为将组合的相位误差应用于至少一个通道锁相环的相位误差输出。 另外，误差信号组合逻辑包括相对于每个信道接收与锁相环相关的信号的误差信息; 组合逻辑，其被配置为组合所接收的误差信号信息并产生组合误差信号，例如用可靠性信息对来自每个信道的接收到的误差信号信息进行加权。 误差补偿输出被配置为将组合的加权误差信号应用于至少一个通道锁相环。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007102996A

公开(公告)日：2007-04-19

申请号：JP2006271101

申请日：2006-10-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ROBERT ALLEN HUTCHINS ,  OELCER SEDAT ,  EVANGELOS S ELEFTHERIOU G

IPC: G11B20/10

CPC classification number: G11B5/09 ,  G11B2005/0013

Abstract: PROBLEM TO BE SOLVED: To provide a dynamic method for asymmetry compensation in a storage read channel. SOLUTION: An asymmetry cancellation component communicates with an analog-to-digital converter which receives an analog signal representing data read from a storage medium by a read head. The asymmetry cancellation component receives the digital signal from the analog-to-digital converter representing the data read from the storage medium, and computes an error signal indicating an asymmetry in the digital signal. The computed error signal is used to determine a coefficient. The digital signal is adjusted using the coefficient to produce a corrected digital signal. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供存储读通道中的不对称补偿的动态方法。 解决方案：不对称消除部件与模数转换器通信，模数转换器接收表示通过读取头从存储介质读取的数据的模拟信号。 不对称消除部件从表示从存储介质读取的数据的数模转换器接收数字信号，并计算指示数字信号不对称的误差信号。 计算出的误差信号用于确定系数。 使用系数调整数字信号以产生校正的数字信号。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006331630A

公开(公告)日：2006-12-07

申请号：JP2006142478

申请日：2006-05-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ELEFTHERIOU EVANGELOS S ,  ROBERT A HUTCHINS ,  OELCER SEDAT

IPC: G11B20/10 ,  G11B5/09

CPC classification number: G11B5/09 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10481 ,  G11B2005/0013 ,  G11B2220/90

Abstract: PROBLEM TO BE SOLVED: To provide a method for an equalizer calculation in a media system using a data set separator sequence.
SOLUTION: An equalizer coefficient generator receives a DSS (data set separator)sequence and a DSS readback sequence being a function of channel processing of the DSS sequence by a read channel. The generator generates a coefficient cyclic equalizer vector as a function of the DSS sequence and DSS readback sequence. Furthermore, the generator generates an error signal as a function for comparing the DSS sequence with the DSS readback sequence based on the coefficient cyclic equalizer vector in equalization. An unacceptable error signal shows the need of adjusting the coefficient cyclic equalizer vector so as to obtain acceptable comparison of the DSS sequence with the DSS readback sequence based on the coefficient cyclic equalizer vector in equalization.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种使用数据集分离器序列在媒体系统中进行均衡器计算的方法。 解决方案：均衡器系数生成器接收DSS（数据集分离器）序列，DSS回读序列是读通道对DSS序列的通道处理的函数。 发生器产生作为DSS序列和DSS回读序列的函数的系数循环均衡器向量。 此外，发生器产生误差信号作为用于基于均衡中的系数循环均衡器向量来比较DSS序列与DSS回读序列的函数。 不可接受的误差信号表示需要调整系数循环均衡器向量，以便基于均衡中的系数循环均衡器向量来获得DSS序列与DSS回读序列的可接受的比较。 版权所有（C）2007，JPO＆INPIT