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    Method of Manufacturing a Semiconductor Device and Semiconductor Device
    52.
    发明申请
    Method of Manufacturing a Semiconductor Device and Semiconductor Device 有权
    制造半导体器件和半导体器件的方法

    公开(公告)号：US20160093731A1

    公开(公告)日：2016-03-31

    申请号：US14868909

    申请日：2015-09-29

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Till Schloesser

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/265 ,  H01L29/40 ,  H01L29/10

    CPC classification number: H01L29/7825 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7835

    Abstract: A method of manufacturing a semiconductor device including a transistor comprises forming field plate trenches in a main surface of a semiconductor substrate, a drift zone being defined between adjacent field plate trenches, forming a field dielectric layer in the field plate trenches, thereafter, forming gate trenches in the main surface of the semiconductor substrate, a channel region being defined between adjacent gate trenches, and forming a conductive material in at least some of the field plate trenches and in at least some of the gate trenches. The method further comprising forming a source region and forming a drain region in the main surface of the semiconductor substrate.

    Abstract translation: 制造包括晶体管的半导体器件的方法包括在半导体衬底的主表面中形成场板沟槽，在相邻的场板沟槽之间限定漂移区，在场板栅沟中形成场介电层，之后形成栅极 在半导体衬底的主表面中的沟槽，沟道区域被限定在相邻栅极沟槽之间，并且在至少一些场板沟槽和至少一些栅极沟槽中形成导电材料。 该方法还包括形成源极区域并在半导体衬底的主表面中形成漏极区域。

    Integrated circuit and method of manufacturing an integrated circuit
    55.
    发明授权
    Integrated circuit and method of manufacturing an integrated circuit 有权
    集成电路和集成电路制造方法

    公开(公告)号：US09129820B2

    公开(公告)日：2015-09-08

    申请号：US13951099

    申请日：2013-07-25

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Markus Zundel ,  Till Schloesser

    IPC: H01L21/00 ,  H01L27/06 ,  H01L49/02

    CPC classification number: H01L27/0805 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/407

    Abstract: An integrated circuit is formed in a semiconductor substrate. The integrated circuit includes a trench formed in a first main surface of the semiconductor substrate. The trench includes a first trench portion and a second trench portion. The first trench portion is connected with the second trench portion. Openings of the first and second trench portions are adjacent to the first main surface. The integrated circuit further includes a trench transistor structure including a gate electrode disposed in the first trench portion, and a trench capacitor structure including a capacitor dielectric and a first capacitor electrode. The capacitor dielectric and the first capacitor electrode are disposed in the second trench portion. The first capacitor electrode includes a layer conformal with a sidewall of the second trench portion.

    Abstract translation: 在半导体衬底中形成集成电路。 集成电路包括形成在半导体衬底的第一主表面中的沟槽。 沟槽包括第一沟槽部分和第二沟槽部分。 第一沟槽部分与第二沟槽部分连接。 第一沟槽部分和第二沟槽部分的开口与第一主表面相邻。 集成电路还包括沟槽晶体管结构，其包括设置在第一沟槽部分中的栅电极和包括电容器电介质和第一电容器电极的沟槽电容器结构。 电容器电介质和第一电容器电极设置在第二沟槽部分中。 第一电容器电极包括与第二沟槽部分的侧壁共形的层。

    INTEGRATED CIRCUIT HAVING AN ESD PROTECTION STRUCTURE AND PHOTON SOURCE
    56.
    发明申请
    INTEGRATED CIRCUIT HAVING AN ESD PROTECTION STRUCTURE AND PHOTON SOURCE 有权
    具有防静电保护结构和光电源的集成电路

    公开(公告)号：US20150249078A1

    公开(公告)日：2015-09-03

    申请号：US14628823

    申请日：2015-02-23

    Applicant: Infineon Technologies AG

    Inventor： Yiqun Cao ,  Ulrich Glaser ,  Magnus-Maria Hell ,  Julien Lebon ,  Michael Mayerhofer ,  Andreas Meiser ,  Matthias Stecher ,  Joost Willemen

    IPC: H01L27/02

    CPC classification number: H01L27/0255 ,  H01L27/0292 ,  H02H9/046

    Abstract: An integrated circuit having an ESD protection structure is described. One embodiment includes a circuit section interconnected with a first terminal and with a second terminal and being operable at voltage differences between the first terminal and second terminal of greater than +10 V and less than −10 V. The integrated circuit additionally includes an ESD protection structure operable to protect the circuit section against electrostatic discharge between the first terminal and the second terminal. The ESD protection structure is operable with voltage differences between the first and second terminals of greater than +10 V and less than −10 V without triggering. The ESD protection structure is electrically and optically coupled to a photon source such that photons emitted by the photon source upon ESD pulse loading are absorbable in the ESD protection structure and an avalanche breakdown is initiatable by electron-hole pairs generated by the absorbed photons.

    Abstract translation: 描述具有ESD保护结构的集成电路。 一个实施例包括与第一端子和第二端子互连的电路部分，并且可在第一端子和第二端子之间的电压差大于+ 10V且小于-10V的情况下工作。集成电路还包括ESD保护 结构可操作以保护电路部分免受第一端子和第二端子之间的静电放电。 ESD保护结构可以在第一和第二端子之间的电压差大于+10V且小于-10V而不触发。 ESD保护结构电光学耦合到光子源，使得在ESD脉冲负载时由光子源发射的光子在ESD保护结构中是可吸收的，并且雪崩击穿可由吸收的光子产生的电子 - 空穴对引发。

    Integrated circuit, semiconductor device and method of manufacturing a semiconductor device
    57.
    发明授权
    Integrated circuit, semiconductor device and method of manufacturing a semiconductor device 有权
    集成电路，半导体器件和制造半导体器件的方法

    公开(公告)号：US09082773B2

    公开(公告)日：2015-07-14

    申请号：US13754240

    申请日：2013-01-30

    Applicant: Infineon Technologies AG

    Inventor： Andreas Meiser ,  Markus Zundel ,  Steffen Thiele

    IPC: H01L27/105 ,  H01L23/544 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234

    CPC classification number: H01L23/544 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/7813 ,  H01L29/7815 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit including a semiconductor device has a power component including a plurality of trenches in a cell array, the plurality of trenches running in a first direction, and a sensor component integrated into the cell array of the power component and including a sensor cell having an area which is smaller than an area of the cell array of the power component. The integrated circuit further includes isolation trenches disposed between the sensor component and the power component, an insulating material being disposed in the isolation trenches. The isolation trenches run in a second direction that is different from the first direction.

    Abstract translation: 包括半导体器件的集成电路具有包括单元阵列中的多个沟槽的功率分量，沿第一方向运行的多个沟槽和集成到功率组件的单元阵列中的传感器组件，并且包括具有 小于电力部件的电池阵列的面积的区域。 集成电路还包括设置在传感器部件和功率部件之间的隔离沟槽，绝缘材料设置在隔离沟槽中。 隔离沟槽沿与第一方向不同的第二方向延伸。

    Semiconductor Device and Method for Producing a Semiconductor Device
    60.
    发明申请
    Semiconductor Device and Method for Producing a Semiconductor Device 有权
    用于制造半导体器件的半导体器件和方法

    公开(公告)号：US20150137226A1

    公开(公告)日：2015-05-21

    申请号：US14548375

    申请日：2014-11-20

    Applicant: Infineon Technologies AG

    Inventor： Till Schloesser ,  Andreas Meiser

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

    CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66734

    Abstract: A semiconductor device includes a semiconductor substrate having first regions of a first conductivity type and body regions of the first conductivity type, which are arranged in a manner adjoining the first region and overlap the latter in each case on a side of the first region which faces a first surface of the semiconductor substrate, and having a multiplicity of drift zone regions arranged between the first regions and composed of a semiconductor material of a second conductivity type, which is different than the first conductivity type. The first regions and the drift zone regions are arranged alternately and form a superjunction structure. The semiconductor device further includes a gate electrode formed in a trench in the semiconductor substrate.

    Abstract translation: 半导体器件包括具有第一导电类型的第一区域和第一导电类型的主体区域的半导体衬底，它们以与第一区域相邻的方式布置，并且在每种情况下与第一区域的第一区域重叠， 半导体衬底的第一表面，并且具有布置在第一区域之间并由与第一导电类型不同的第二导电类型的半导体材料构成的多个漂移区域。 第一区域和漂移区域交替布置并形成超结构结构。 半导体器件还包括形成在半导体衬底中的沟槽中的栅电极。

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