公开(公告)号：DE60203039T2

公开(公告)日：2006-01-12

申请号：DE60203039

申请日：2002-07-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CLARA MARTIN ,  WIESBAUER ANDREAS

IPC: G11C27/02 ,  H03K17/06 ,  H03K17/687

Abstract: Switched level-shift circuit for a signal-switch (1) which is provided for switching an applied analog input signal (VAIN), wherein the switched level-shift circuit (5) comprises an input terminal (13) for the analog input signal applied to the signal-switch (1), a control input terminal (18) for a control signal (SW), an analog level-shift circuit (15) which adds a constant voltage to the analog input signal (VAIN) to generate a level-shifted analog output signal when the control signal (SW) is in a first logical state (high); and an output terminal (4) for the generated level-shifted analog output signal which is connected to a gate terminal (2) of said signal-switch (1).

公开(公告)号：DE10217855B4

公开(公告)日：2005-12-01

申请号：DE10217855

申请日：2002-04-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WIESBAUER ANDREAS ,  KAHL ALEXANDER ,  CLARA MARTIN

IPC: H03F3/08 ,  H04B10/69 ,  H04L25/26 ,  H03F3/45 ,  H04B10/06

公开(公告)号：DE10342057B4

公开(公告)日：2005-10-20

申请号：DE10342057

申请日：2003-09-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DI GIANDOMENICO ANTONIO ,  WIESBAUER ANDREAS ,  CLARA MARTIN

IPC: G06F7/50 ,  H03M1/12 ,  H03M1/74 ,  H03M3/00 ,  H03M3/02 ,  H03M3/04

公开(公告)号：DE10350594A1

公开(公告)日：2005-06-16

申请号：DE10350594

申请日：2003-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RICHTER HELMUT ,  POETSCHER THOMAS ,  CLARA MARTIN ,  WIESBAUER ANDREAS

IPC: H03M1/10 ,  H03M1/74

Abstract: During an operating phase, a cell current (CC) is formed by the sum of a current in a mirror transistor (MT) (11) with a further current in a calibrating transistor (CT) (15) linked in parallel to the MT. The CC can be picked up on an output node point (1) for a current cell (10p). The CT is connected as a diode during a calibration phase. Independent claims are also included for the following: (A) A digital-analog converter circuit with current cells for generating an analog output signal by relying on an incoming digital signal; (B) and for a sigma-delta modulator circuit with a digital-analog converter circuit.

公开(公告)号：DE10048419C2

公开(公告)日：2003-07-24

申请号：DE10048419

申请日：2000-09-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CLARA MARTIN ,  WIESBAUER ANDREAS ,  STRAEUSNIGG DIETMAR

IPC: H03M1/06 ,  H03M1/12

公开(公告)号：DE10158244A1

公开(公告)日：2003-06-26

申请号：DE10158244

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CLARA MARTIN ,  WIESBAUER ANDREAS

IPC: H01L27/02 ,  H02H9/04 ,  H02M3/156 ,  H02H7/20

Abstract: A high-voltage circuit (HVC) (100) is set up to apply an excess voltage (101) to supply circuit units. A low-voltage (LV) device (116) with a LV circuit (115) is set up to run LV circuit functions. Also, a source (114) of voltage protection sets up a protection voltage (113). A protective device (PD) (111) to protect the low-voltage (LV) device from damage through excess voltage on the high-voltage circuit (HVC) connects so that the PD connects in series between the HVC and the LV device. An Independent claim is also included for a device for protecting low-voltage devices working with a high-voltage circuit against damage through excess voltage on a high-voltage circuit.

公开(公告)号：DE10121716A1

公开(公告)日：2002-11-14

申请号：DE10121716

申请日：2001-05-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CLARA MARTIN ,  WIESBAUER ANDREAS ,  KAHL ALEXANDER ,  TROJER MARTIN

IPC: H04L25/06

Abstract: The arrangement has a signal processor (8,10-13) with a signal input, signal output and auxiliary parameter input and a digital to analog converter (3,4) or DAC for producing the auxiliary parameter whose analog output is connected to the signal processor's auxiliary parameter input. An auxiliary parameter determination device (5,6) has an input connected to signal processor's signal output and an output connected to the DAC's digital input. AN Independent claim is also included for the following: a signal evaluation circuit

公开(公告)号：DE10121715A1

公开(公告)日：2002-11-14

申请号：DE10121715

申请日：2001-05-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CLARA MARTIN ,  WIESBAUER ANDREAS ,  KAHL ALEXANDER ,  TROJER MARTIN

IPC: H04L25/06

Abstract: Interfering offset voltages can occur, particularly in optical data transmission networks, in the case of direct voltage-coupled receive circuits and can stem from a level of background noise of the transmitters of the light signals. Additionally, due to different transmission paths, the amplitudes of the information signals can vary greatly so that, according to amplitude, a different threshold value for a comparator circuit (8) is required for recovering the bit sequence. In order to rectify this drawback, a first step is used during which the direct component is measured at the input or output of an amplifying circuit (3) and, according to this measurement, a correction value is formed for offset compensation. In a second step and in the case of a correction value applied to the output of the amplifying circuit (3), another measurement of the information signal is carried out in order to determine an appropriate threshold value for the comparator circuit (8). The correction value or the threshold value is established at each transmitter and is stored in a storage arrangement (18, 19). In order to evaluate the information signal of a specific transmitter, the correction value or threshold value stored for this transmitter is applied to the amplifying circuit (3) or to the comparator circuit (8) by means of two digital-analog converters (14, 16).