公开(公告)号：DE10126115A1

公开(公告)日：2002-12-19

申请号：DE10126115

申请日：2001-05-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  DORTU JEAN-MARC ,  TAEUBER ANDREAS ,  SCHMOELZ PAUL

IPC: G11C7/10 ,  G11C11/407

Abstract: A data output interface, in particular for semiconductor memories, provides a plurality of output drivers for providing data output signals in a manner dependent on a read command and a clock signal. In order to signal to a microprocessor that can be connected to the data output that data are provided, a data provision signal is additionally provided by a further output driver. The arrangement described can preferably be used for DDR-SDRAMs and enables particularly high clock frequencies.

公开(公告)号：DE10115817A1

公开(公告)日：2002-10-10

申请号：DE10115817

申请日：2001-03-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TAEUBER ANDREAS ,  DORTU JEAN-MARC ,  SCHMOELZ PAUL ,  FEURLE ROBERT

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/407

Abstract: The integrated memory chip has an external control terminal, a dynamic memory, and a control circuit for controlling a memory access to the dynamic memory. The control circuit is connected to the external control terminal, for receiving an access command indicating the beginning of a memory access. The control circuit further has an output, which is connected to the dynamic memory, for outputting at least one activation signal, read command or write command and precharge command generated from the access command. This makes it possible, in the case of use in a data processing system, to dispense with a DRAM controller provided outside the memory chip.

公开(公告)号：DE19944248C2

公开(公告)日：2002-04-11

申请号：DE19944248

申请日：1999-09-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT

IPC: H03K19/0175 ,  G11C11/4093 ,  H03K3/3565 ,  H03K19/00

Abstract: An integrated semiconductor circuit has two modes of operation and has several input buffers (IB1;IBn) which each have a terminal for an input signal (IN1;INn), and has at least one input buffer (IB1) for controlling switch-over between the operating modes through its input signal. The input buffer (IB1) for controlling the switch-over of the operating modes has a driver circuit (10) with an inverter circuit (11) which can be operated depending on requirements, in the first and second operating mode. The remaining input buffers (IB2;IBn) each has a difference amplifier circuit (DA) which is switched off in the second operating mode. The first operating mode is specifically used for normal operation and the second operating mode for current-saving operation of the semiconductor circuit (1).

公开(公告)号：DE10045692A1

公开(公告)日：2002-04-04

申请号：DE10045692

申请日：2000-09-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE

IPC: G11C11/401 ,  G11C11/34 ,  G11C11/407 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/404 ,  G11C8/00 ,  G11C5/14

Abstract: An integrated store, has storage cells which each comprise a selection transistor and a storage capacitance with each storage cell, the storage capacitance is connected via the selection transistor to one of several column lines (BLK). With each storage cell, a control terminal of the selection transistor is connected to one of several row-lines (WLN) and with the buffer capacitances in each case one contact (K2) is connected to a further one of the column lines (BLK) and the buffer capacitances (CP) are arranged in such a way that the connections (GB) between the respective buffer capacitance and the contact (K2) is arranged parallel to another one of the row-lines (WLK).

公开(公告)号：DE19960247A1

公开(公告)日：2001-06-21

申请号：DE19960247

申请日：1999-12-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SCHNEIDER HELMUT

IPC: G11C7/10 ,  G11C7/20 ,  G11C11/00 ,  G11C11/4091 ,  G11C11/56 ,  G11C14/00 ,  G11C11/4063 ,  G11C29/00

Abstract: The invention relates to a data storage device, comprising a plurality of storage cells for storing data which are represented by a first physical value of the storing storage elements of the storage cells, especially their conductivity or charge, said storage elements being configured especially in the form of a storage capacitor. A detection device is provided for detecting the first physical value representing the data and a second detection device is provided for detecting a second physical value of the storage cells or constituents of the same, especially of the storage element, especially the leakage current of the storage capacitor provided for storing the data. Said second physical value represents a second detectable item of information in addition to the first physical value representing the data, independently of said first physical value . The invention also relates to a method for permanently storing information in storage cells of a data storage device for reversibly or permanently storing data.

公开(公告)号：DE19948570A1

公开(公告)日：2001-04-19

申请号：DE19948570

申请日：1999-10-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SCHNEIDER HELMUT

IPC: G03F1/00 ,  H01L21/768 ,  H01L23/522

Abstract: An arrangement for wiring of conductor paths (1-4) fabricated by the use of phase-masks with alternating phase on a given metallisation plane, such that a first conductor path (2) fabricated with a phase-mask of a first phase is adjacent to a second conductor path (3') fabricated with a phase-mask of a second phase, opposite to the first phase, so that a discontinuity in the wiring formed from the first and the second conductor paths (2,3'), results at the point of connection between the first (2) and the second (3') conductor paths. The connection between the first (2) and the second (3') conductor paths is achieved through a connection contact (7) located underneath or above the specified metallisation plane, the connection contact consisting specifically of doped polycrystalline silicon.