公开(公告)号：DE102008017282A1

公开(公告)日：2008-10-30

申请号：DE102008017282

申请日：2008-04-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAKOSCHKE RONALD ,  NIRSCHL THOMAS

IPC: H01L27/24

公开(公告)号：DE102005029493A1

公开(公告)日：2006-02-23

申请号：DE102005029493

申请日：2005-06-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAKOSCHKE RONALD ,  NIRSCHL THOMAS ,  SCHRUEFER KLAUS ,  SHUM DANNY PAK-CHUM

IPC: G11C16/04 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/861

Abstract: A method of fabricating a memory device in a semiconductor substrate, the device having a memory array having a plurality of memory cell transistors arranged in rows and columns. The method includes forming a plurality of tunneling field effect transistors, forming a first well of the second doping type, forming a second well of the first doping type surrounding the first well, forming a first word line connected to a first row of memory cell transistors, forming a first bit line to control a voltage of doped drain regions of tunneling field effect transistors of a first column of memory cell transistors, and forming a second bit line parallel to the first bit line.

公开(公告)号：DE10321742A1

公开(公告)日：2004-12-09

申请号：DE10321742

申请日：2003-05-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULER FRANZ ,  KAKOSCHKE RONALD

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115

公开(公告)号：DE10321740A1

公开(公告)日：2004-12-09

申请号：DE10321740

申请日：2003-05-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMPEL GEORG ,  SCHULER FRANZ ,  KAKOSCHKE RONALD

IPC: H01L21/8246 ,  H01L21/8247 ,  H01L27/115

公开(公告)号：DE10240436C1

公开(公告)日：2003-12-18

申请号：DE10240436

申请日：2002-09-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMPEL GEORG ,  SHUM DANNY ,  KAKOSCHKE RONALD

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L23/528 ,  H01L21/768

Abstract: Bit line structure comprises a surface bit line for joining a number of first doping regions above a substrate surface, a trenched bit line for joining a number of second doping regions within the substrate (1, 2, 3), a trench isolation layer (6) on a surface of a trench, a covering isolation layer (9) on the trenched bit line in a first upper partial region of the trench, a number of covering connecting layers (12) on the trenched bit line in a second partial region of the trench, and a number of self-adjusting connecting layers (13) in the region of the substrate surface. The covering connecting layers are electrically connected to the second doping regions via the self-adjusting connecting layers. An Independent claim is also included for a process for the production of a bit line structure.