公开(公告)号：JP2006054435A

公开(公告)日：2006-02-23

申请号：JP2005198146

申请日：2005-07-06

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： KAKOSCHKE RONALD ,  NIRSCHL THOMAS ,  SCHRUEFER KLAUS ,  SHUM DANNY PAK-CHUM

IPC: H01L21/8247 ,  G11C16/04 ,  H01L21/8244 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/11 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861

CPC classification number: G11C16/0416 ,  H01L27/115 ,  H01L29/8616

Abstract: PROBLEM TO BE SOLVED: To provide a memory device which can be easily manufactured and whose cell size can be shrunk.
SOLUTION: The memory device, in which tunnel field-effect transistors (TFET) and embedded bit lines are used, includes a matrix containing a plurality of rows and columns of memory cells. Each memory cell includes at least one cell transistor (T01 to Tmn). The cell transistor includes a first doped region and a second doped region, wherein the one is a source region (98) and the other is a drain region (152). The memory device includes a plurality of word lines (WL0 to WLn). Each word line is connected to the memory cells belonging to the row and to the bit lines, while each bit line is connected to the memory cells belonging to the column. The doping type of the first doped region and that of the second doping region are different.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供可以容易地制造并且其单元尺寸可以缩小的存储器件。 解决方案：使用隧道场效应晶体管（TFET）和嵌入式位线的存储器件包括包含多个行和列的存储器单元的矩阵。 每个存储单元包括至少一个单元晶体管（T01至Tmn）。 单元晶体管包括第一掺杂区和第二掺杂区，其中一个是源极区（98），另一个是漏极区（152）。 存储装置包括多个字线（WL0〜WLn）。 每个字线连接到属于行和位线的存储单元，而每个位线连接到属于该列的存储单元。 第一掺杂区域和第二掺杂区域的掺杂类型不同。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2004032201A3

公开(公告)日：2004-06-10

申请号：PCT/EP0310218

申请日：2003-09-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MAHNKOPF REINHARD ,  NEUMUELLER WALTER ,  PRIGGE ODIN ,  SCHAFBAUER THOMAS ,  SCHRUEFER KLAUS

IPC: H01L21/266 ,  H01L21/74 ,  H01L21/8238

CPC classification number: H01L21/743 ,  H01L21/266 ,  H01L21/74 ,  H01L21/823878 ,  H01L21/823892

Abstract: A method of fabricating a semiconductor connective region of a first conductivity type through a semiconductor layer of a second conductivity type which at least partly separates a bulk portion of semiconductor body (substrate) of the first conductivity type from a semiconductor well of the first conductivity type includes a step of implanting ions into a portion of the layer to convert the conductivity of the implanted portion to the first conductivity type. This electrically connects the well to the bulk portion of the body. Any biasing potential applied to the bulk portion of the body is thus applied to the well. This eliminates any need to form a contact in the well for biasing the well and thus allows the well to be reduced in size.

Abstract translation: 一种通过第二导电类型的半导体层制造第一导电类型的半导体连接区域的方法，该半导体层至少部分地将第一导电类型的半导体本体（衬底）的主体部分与第一导电类型的半导体阱分开 包括将离子注入该层的一部分以将注入部分的导电率转换为第一导电类型的步骤。 这将井与本体的主体部分电连接。 因此，施加到身体的主体部分的任何偏置电位被施加到井。 这消除了在井中形成用于偏压井的接触的任何需要，从而允许井的尺寸减小。

公开(公告)号：DE102008035707A1

公开(公告)日：2009-02-19

申请号：DE102008035707

申请日：2008-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAKOSCHKE RONALD ,  SCHRUEFER KLAUS

IPC: H01L27/06 ,  H01L21/331 ,  H01L21/8249

公开(公告)号：DE10360874A1

公开(公告)日：2005-07-28

申请号：DE10360874

申请日：2003-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHRUEFER KLAUS

IPC: H01L29/786 ,  H01L29/80 ,  H01L29/78 ,  H01L21/336

Abstract: A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.

公开(公告)号：DE102008038552A1

公开(公告)日：2009-04-16

申请号：DE102008038552

申请日：2008-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JENEI SNEZANA ,  PACHA CHRISTIAN ,  RUSS CHRISTIAN ,  SCHRUEFER KLAUS

IPC: H01L29/861 ,  H01L21/329

Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

公开(公告)号：DE102005007822A1

公开(公告)日：2006-08-31

申请号：DE102005007822

申请日：2005-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NIRSCHL THOMAS ,  PACHA CHRISTIAN ,  SCHULZ THOMAS ,  SCHMITT-LANDSIEDEL DORIS ,  HOLZ JUERGEN ,  SCHRUEFER KLAUS ,  KAKOSCHKE RONALD

IPC: H01L27/115

公开(公告)号：DE102009049774A1

公开(公告)日：2010-08-19

申请号：DE102009049774

申请日：2009-06-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUSS CHRISTIAN ,  PACHA CHRISTIAN ,  JENEI SNEZANA ,  SCHRUEFER KLAUS

IPC: H01L21/8249 ,  H01L21/84 ,  H01L23/60 ,  H01L27/06 ,  H01L27/082 ,  H01L27/085 ,  H01L27/12

Abstract: Ausführungsformen betreffen eine BiCMOS-Schaltungsanordnung, welche mindestens zwei Schaltungsstufen aufweist, wobei eine erste Schaltungsstufe von den mindestens zwei Schaltungsstufen mit einem Eingangsanschluss der Schaltungsanordnung elektrisch gekoppelt ist, wobei eine zweite Schaltungsstufe von den mindestens zwei Schaltungsstufen mit einem Ausgangsanschluss der Schaltungsanordnung elektrisch gekoppelt ist, wobei eine Schaltungsstufe von der ersten Schaltungsstufe und der zweiten Schaltungsstufe ein erstes SEG-Bipolarbauelement aufweist, und wobei die jeweils andere Schaltungsstufe der ersten Schaltungsstufe und der zweiten Schaltungsstufe ein zweites SEG-Bipolarbauelement oder ein MOS-Bauelement aufweist.

公开(公告)号：DE102005029493A1

公开(公告)日：2006-02-23

申请号：DE102005029493

申请日：2005-06-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAKOSCHKE RONALD ,  NIRSCHL THOMAS ,  SCHRUEFER KLAUS ,  SHUM DANNY PAK-CHUM

IPC: G11C16/04 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/861

Abstract: A method of fabricating a memory device in a semiconductor substrate, the device having a memory array having a plurality of memory cell transistors arranged in rows and columns. The method includes forming a plurality of tunneling field effect transistors, forming a first well of the second doping type, forming a second well of the first doping type surrounding the first well, forming a first word line connected to a first row of memory cell transistors, forming a first bit line to control a voltage of doped drain regions of tunneling field effect transistors of a first column of memory cell transistors, and forming a second bit line parallel to the first bit line.

公开(公告)号：DE102009024756A1

公开(公告)日：2010-01-28

申请号：DE102009024756

申请日：2009-06-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUSS CHRISTIAN ,  PACHA CHRISTIAN ,  JENEI SNEZANA ,  SCHRUEFER KLAUS

IPC: H01L29/732 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/07

Abstract: The fin-type bipolar transistor has a fin structure that is formed in the main region of transistor. A terminal region is formed on a portion of main region such that the terminal region is formed as an epitaxially grown region. Independent claims are included for the following: (1) method for producing bipolar transistor; (2) vertically integrated electronic device; (3) method for producing vertically integrated electronic device; (4) bipolar complementary metal oxide semiconductor (BiCMOS) circuit arrangement; and (5) method for fabricating BiCMOS circuit arrangement.

公开(公告)号：DE102006027178A1

公开(公告)日：2007-07-05

申请号：DE102006027178

申请日：2006-06-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PACHA CHRISTIAN DR ,  ARNIM KLAUS VON ,  BERTHOLD JOERG ,  SCHRUEFER KLAUS

IPC: H01L27/088 ,  H01L21/8234

Abstract: In a first embodiment, a multi-fin component arrangement has a plurality of multi-fin component partial arrangements. Each of the multi-fin component partial arrangements has a plurality of electronic components, which electronic components have a multi-fin structure. At least one multi-fin component partial arrangement has at least one dummy structure, which at least one dummy structure is formed between at least two of the electronic components formed in the at least one multi-fin component partial arrangement. The dummy structure is formed in such a way that electrical characteristics of the electronic components formed in the multi-fin component partial arrangements are adapted to one another.