公开(公告)号：EP2588958A4

公开(公告)日：2016-11-02

申请号：EP11804047

申请日：2011-06-22

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  HU SHILIANG ,  BORIN EDSON ,  WANG CHENG C ,  BRETERNITZ MAURICIO JR ,  LIU WEI

IPC: G06F9/46 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/30076 ,  G06F9/30174 ,  G06F9/3879 ,  G06F9/4893 ,  Y02D10/24

Abstract: An apparatus and method is described herein for coupling a processor core of a first type with a co-designed core of a second type. Execution of program code on the first core is monitored and hot sections of the program code are identified. Those hot sections are optimize for execution on the co-designed core, such that upon subsequently encountering those hot sections, the optimized hot sections are executed on the co-designed core. When the co-designed core is executing optimized hot code, the first processor core may be in a low-power state to save power or executing other code in parallel. Furthermore, multiple threads of cold code may be pipelined on the first core, while multiple threads of hot code are pipeline on the co-designed core to achieve maximum performance.

公开(公告)号：EP2956853A4

公开(公告)日：2016-10-19

申请号：EP14775994

申请日：2014-03-27

Applicant: INTEL CORP

Inventor： RONG HONGBO ,  PARK HYUNCHUL ,  WU YOUFENG

IPC: G06F9/38 ,  G06F9/45 ,  G06F9/46

CPC classification number: G06F8/4452 ,  G06F8/433

公开(公告)号：EP2901289A4

公开(公告)日：2016-04-13

申请号：EP13840642

申请日：2013-09-19

Applicant: INTEL CORP

Inventor： CHUNG JAEWOONG ,  WU YOUFENG ,  WANG CHENG

IPC: G06F12/08 ,  G06F9/00 ,  G06F9/45 ,  G06F9/455 ,  G06F12/02

CPC classification number: G06F12/0888 ,  G06F9/4552 ,  G06F12/0246 ,  G06F12/0897 ,  G06F2212/452

Abstract: Methods and apparatus are disclosed to cache code in non-volatile memory. A disclosed example method includes identifying an instance of a code request for first code, identifying whether the first code is stored on non-volatile (NV) random access memory (RAM) cache, and when the first code is absent from the NV RAM cache, adding the first code to the NV RAM cache when a first condition associated with the first code is met and preventing storage of the first code to the NV RAM cache when the first condition is not met.

Abstract translation: 的方法和设备是光盘的非易失性存储器，以游离缺失高速缓存的代码。 一种盘游离缺失实施例的方法包括在用于第一码的代码请求的实例标识，标识是否所述第一代码存储在非易失性（NV）的随机存取存储器（RAM）高速缓存，并且当所述第一代码是从所述NV RAM缓存不存在 ，将所述第一代码到NV RAM缓存当与第一代码相关联的第一条件被满足，并且当第一条件不被满足防止第一代码到NV RAM缓存的存储。

公开(公告)号：EP2761478A4

公开(公告)日：2015-10-28

申请号：EP11873137

申请日：2011-09-29

Applicant: INTEL CORP

Inventor： WANG CHENG ,  WU YOUFENG ,  CHUNG JAEWOONG

IPC: G06F13/14 ,  G06F9/30 ,  G06F12/00

CPC classification number: G06F3/065 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3863

公开(公告)号：EP2588959A4

公开(公告)日：2014-04-16

申请号：EP11804093

申请日：2011-06-27

Applicant: INTEL CORP

Inventor： LIU WEI ,  WU YOUFENG

IPC: G06F9/46 ,  G06F9/06 ,  G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/3834 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3851 ,  G06F9/52

公开(公告)号：EP3123341A4

公开(公告)日：2017-10-25

申请号：EP15769489

申请日：2015-03-26

Applicant: INTEL CORP

Inventor： WANG CHENG ,  WU YOUFENG ,  RONG HONGBO ,  PARK HYUNCHUL

IPC: G06F13/10 ,  G06F9/44 ,  G06F9/455

CPC classification number: G06F9/45516 ,  G06F9/4411 ,  G06F9/4552 ,  G06F13/10

Abstract: In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed.

公开(公告)号：EP2695061A4

公开(公告)日：2017-05-17

申请号：EP11863199

申请日：2011-11-29

Applicant: INTEL CORP

Inventor： WANG CHENG ,  WU YOUFENG

IPC: G06F9/50 ,  G06F9/06 ,  G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/3838 ,  G06F9/384

公开(公告)号：EP2619654A4

公开(公告)日：2016-11-16

申请号：EP11827728

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  WANG CHENG ,  BORIN EDSON ,  HU SHILIANG ,  ZILLES CRAIG B

IPC: G06F9/45 ,  G06F9/06 ,  G06F9/30 ,  G06F9/305 ,  G06F15/76

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Abstract translation: 的装置和方法被描述为有条件地提交和/或推测检查点的交易，这潜在地导致了交易的动态调整。 在二进制代码动态优化，交易被插入到内存提供保障顺序，使动态优化，以更积极的优化代码。 和条件提交启用动态优化代码的执行效率，同时努力避免用尽硬件资源的交易。 虽然投机性的检查站时能交易的中止快速高效的恢复。 处理器硬件angepasst支持交易的动态调整，为寻求包括解码器确实承认条件提交指令，推测检查点指令，或两者兼而有之。 和处理器的硬件是执行操作，以支持条件提交或推测检查点的响应于解码请示此外angepasst。

公开(公告)号：EP2619655A4

公开(公告)日：2015-03-04

申请号：EP11827755

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

IPC: G06F9/30 ,  G06F9/06 ,  G06F9/38 ,  G06F9/45

CPC classification number: G06F9/3842 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3857

公开(公告)号：EP2494468A4

公开(公告)日：2013-11-20

申请号：EP10828698

申请日：2010-08-25

Applicant: INTEL CORP

Inventor： BLOMSTEDT JOSEPH ,  WANG CHENG ,  WU YOUFENG

IPC: G06F17/21 ,  G06F9/30 ,  G06F9/38 ,  G06F9/45 ,  G06F11/36 ,  G06F13/14

CPC classification number: G06F11/3604 ,  G06F8/433 ,  G06F8/456

Abstract: In one embodiment of the invention a method comprising (1) receiving an unstructured binary code region that is single-threaded; (2) determining a slice criterion for the region; (3) determining a call edge, a return edge, and a fallthrough pseudo-edge for the region based on analysis of the region at a binary level; and (4) determining a context-sensitive slice based on the call edge, the return edge, the fallthrough pseudo-edge, and the slice criterion. Embodiments of the invention may include a program analysis technique that can be used to provide context-sensitive slicing of binary programs for slicing hot regions identified at runtime, with few underlying assumptions about the program from which the binary is derived. Also, in an embodiment a slicing method may include determining a context-insensitive slice, when a time limit is met, by determining the context-insensitive slice while treating call edges as a normal control flow edges.