公开(公告)号：US20250105074A1

公开(公告)日：2025-03-27

申请号：US18977572

申请日：2024-12-11

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Wei Wei ,  Jose Fernando Waimin Almendares ,  Ryan Joseph Carrazzone ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Dingying Xu ,  Hongxia Feng ,  Yiqun Bai ,  Hiroki Tanaka ,  Brandon Christian Marin ,  Jeremy Ecton ,  Benjamin Taylor Duong ,  Gang Duan ,  Srinivas Venkata Ramanuja Pietambaram ,  Rui Zhang ,  Mohit Gupta

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498

Abstract: Glass cores including protruding through glass vias and related methods are disclosed herein. An example substrate disclosed herein includes a glass core including a surface and a copper through glass via (TGV) extending through the glass core, the TGV including a protrusion extending from the surface.

公开(公告)号：US20250062206A1

公开(公告)日：2025-02-20

申请号：US18451150

申请日：2023-08-17

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Gang Duan ,  Srinivas V. Pietambaram ,  Jeremy Ecton

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments of a semiconductor die comprise: a first bond-pad on a first surface to couple to a package substrate, a second bond-pad on a second surface, the second surface being opposite to the first surface, a hole through the semiconductor die, a conductive pillar within the hole separated from sidewalls of the hole by an air gap, the conductive pillar coupled to the first bond-pad and the second bond-pad, and pathways conductively coupling at least two integrated circuit (IC) dies proximate to the second surface.

公开(公告)号：US12224103B2

公开(公告)日：2025-02-11

申请号：US17348580

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Matthew Tingey ,  Ravindranath Mahajan ,  Srinivas Pietambaram

IPC: H05K1/02 ,  G11B5/17 ,  H01F17/02 ,  H01F27/23 ,  H01F27/28 ,  H01F27/32 ,  H01L21/822 ,  H01L23/498 ,  H01L25/16 ,  H01L25/18 ,  H01L27/01 ,  H01L27/04 ,  H01L27/32 ,  H05K3/28

Abstract: An electronic substrate may be fabricated having a dielectric material, metal pads embedded in the dielectric material with co-planar surfaces spaced less than one tenth millimeter from each other, and a metal trace embedded in the dielectric material and attached between the metal pads, wherein a surface of the metal trace is non-co-planar with the co-planar surfaces of the metal pads at a height of less than one millimeter, and wherein sides of the metal trace are angled relative to the co-planar surfaces of the metal pads. In an embodiment of the present description, an embedded angled inductor may be formed that includes the metal trace. In an embodiment, an integrated circuit package may be formed with the electronic substrate, wherein at least one integrated circuit devices may be attached to the electronic substrate. Other embodiments are disclosed and claimed.

公开(公告)号：US20240347402A1

公开(公告)日：2024-10-17

申请号：US18756679

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon Christian Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Leonel Arana ,  Benjamin Duong

IPC: H01L23/13 ,  H01L23/15 ,  H01L25/065

CPC classification number: H01L23/13 ,  H01L23/15 ,  H01L25/0655

Abstract: Methods and apparatus to reduce delamination in hybrid cores are disclosed. An example hybrid core of an integrated circuit (IC) package comprises a frame, and a glass panel including a top surface, an edge adjacent the frame, and a tapered surface extending between the edge and the top surface.

公开(公告)号：US20240329339A1

公开(公告)日：2024-10-03

申请号：US18191273

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Changhua Liu ,  Hiroki Tanaka ,  Brandon C. Marin ,  Srinivas V. Pietambaram

IPC: G02B6/42 ,  G02B6/38

CPC classification number: G02B6/4228 ,  G02B6/3886 ,  G02B6/4239 ,  G02B6/4292

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a photonic integrated circuit (PIC) having a first surface having a channel and a first magnetic material; a fiber connector including a second surface with a second magnetic material; and a fiber physically coupled to the second surface of the fiber connector by an adhesive material; wherein the first surface of the PIC is coupled to the second surface of the fiber connector by the first and second magnetic materials with the fiber positioned in the channel.

公开(公告)号：US20240224543A1

公开(公告)日：2024-07-04

申请号：US18091264

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton

IPC: H10B80/00 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498

CPC classification number: H10B80/00 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827

Abstract: Multi-chip/die device including a logic IC die facing a first side of a glass substrate and a memory IC die facing, and coupled to, the logic IC die. First ones of first metallization features of the logic IC die are coupled to through-glass vias extending through a thickness of the glass substrate. The memory IC die is coupled to second ones of the first metallization features, either directly or by way of other through-glass vias. The logic IC die and/or memory IC die may be directly bonded to the through-glass vias or may be attached by solder. The logic IC die or memory IC die may be embedded within the glass substrate. Through-glass vias within a region beyond an edge of the memory IC die may couple the logic IC die to a host component either through a routing structure built up adjacent the memory IC die, or through solder features attached to the glass substrate adjacent to the memory IC die.

公开(公告)号：US20240222219A1

公开(公告)日：2024-07-04

申请号：US18090883

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Suddhasattwa Nad ,  Jeremy Ecton ,  Yang Wu ,  Minglu Liu ,  Yosuke Kanaoka

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/42 ,  H01L23/48 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L23/367 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/42 ,  H01L23/481 ,  H01L23/5381 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253

Abstract: Microelectronic integrated circuit package structures include a first die and a second die both coupled to a bridge structure at an interface. A first thermally conductive mold material is on a first side of the interface and surrounds the first die and the second die. A second mold material is on a second, opposing side of the interface and surrounds the bridge structure.

公开(公告)号：US20240219645A1

公开(公告)日：2024-07-04

申请号：US18090253

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram

IPC: G02B6/35

CPC classification number: G02B6/356 ,  G02B6/3596 ,  G02B6/3598

Abstract: An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.

公开(公告)号：US20240176085A1

公开(公告)日：2024-05-30

申请号：US18059074

申请日：2022-11-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: G02B6/43 ,  G02B6/122 ,  G02B6/30

CPC classification number: G02B6/43 ,  G02B6/122 ,  G02B6/30

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include a substrate having a core with a surface, wherein a material of the core includes glass; and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (PIC) electrically coupled to the conductive pathways in the dielectric material; a first optical component between the PIC and the surface of the core, wherein the first optical component is along a perimeter of the core; and a second optical component coupled to the first optical component, wherein the second optical component is optically coupled to the PIC by an optical pathway through the first optical component.

公开(公告)号：US20240128181A1

公开(公告)日：2024-04-18

申请号：US18047033

申请日：2022-10-17

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Hiroki Tanaka ,  Haobo Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/32 ,  H01L2924/15311

Abstract: Embodiments of a microelectronic assembly that includes: a package substrate comprising a plurality of layers of organic dielectric material and conductive traces alternating with conductive vias in alternate layers of the organic dielectric material; and a plurality of integrated circuit dies coupled to a first side of the package substrate by interconnects, in which: the plurality of layers of the organic dielectric material comprises at least a first layer having a conductive via and a second layer having a conductive trace in contact with the conductive via, the second layer is not coplanar with the first layer, sidewalls of the conductive via are orthogonal to the conductive trace, and two opposing sidewalls of the conductive via separated by a width of the conductive via protrude from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via.