公开(公告)号：US11501484B2

公开(公告)日：2022-11-15

申请号：US17032964

申请日：2020-09-25

Applicant: INTEL CORPORATION

Inventor： Michael Apodaca ,  Carsten Benthin ,  Kai Xiao ,  Carson Brownlee ,  Timothy Rowley ,  Joshua Barczak ,  Travis Schluessler

IPC: G06T15/06 ,  G06F16/901 ,  G06F7/14 ,  G06F9/38 ,  G06N3/02 ,  G06T5/00 ,  G06T1/20 ,  G06T1/60

Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.

公开(公告)号：US11494867B2

公开(公告)日：2022-11-08

申请号：US17115555

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Michael Apodaca ,  Aditya Navale ,  Travis Schluessler ,  Vamsee Vardhan Chivukula ,  Abhishek Venkatesh ,  Subramaniam Maiyuran

IPC: G06T1/20

Abstract: An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.

公开(公告)号：US20210304351A1

公开(公告)日：2021-09-30

申请号：US17323818

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Charles Moidel ,  Michael Apodaca ,  Murali Ramadoss

IPC: G06T1/20 ,  G06F9/50 ,  G06N20/00 ,  G06N3/08 ,  G06T1/60 ,  G06F9/46

Abstract: Described herein are devices, systems and methods to utilize non-volatile memory to save and retrieve data that is used to accelerate the load and resume of GPU accelerated applications. Non-volatile memory and GPU logic are configured to enable the GPU to directly access the non-volatile memory to enable data to be read without requiring the data to traverse the CPU and CPU memory. This data access path creates a faster method for loading data into GPU local memory.

公开(公告)号：US20210287420A1

公开(公告)日：2021-09-16

申请号：US17206584

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Devan Burke ,  Abhishek Venkatesh ,  Travis Schluessler

IPC: G06T15/04 ,  G06T15/00 ,  G06T15/80

Abstract: One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value. The resolve can be a stenciled resolve that automatically bypasses execution of a pixel shader for pixels having clear color data.

公开(公告)号：US20210012452A1

公开(公告)日：2021-01-14

申请号：US16943984

申请日：2020-07-30

Applicant: Intel Corporation

Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

IPC: G06T1/20 ,  G06T17/10

Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

公开(公告)号：US10733693B2

公开(公告)日：2020-08-04

申请号：US16208715

申请日：2018-12-04

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Michael Apodaca ,  Jason Surprise ,  Peter Doyle

IPC: G06T15/10 ,  G06T1/20 ,  G06F9/50

Abstract: Embodiments described herein provide data processing device comprising a processor, a memory, and a large draw monitor comprising a processing unit to determine whether a vertex count for a graphics workload exceeds a threshold value, and in response to a determination that the vertex count for the graphics workload exceeds the threshold value, to divide the graphics workload over graphics processing units instantiated on multiple separate tiles. Other embodiments may be described and claimed.

公开(公告)号：US20190266069A1

公开(公告)日：2019-08-29

申请号：US15903393

申请日：2018-02-23

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  Elmoustapha Ould-Ahmed-Vall ,  John Gierach ,  Tomer Bar On ,  Devan Burke

IPC: G06F11/36 ,  G06F9/38

Abstract: In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.

公开(公告)号：US20190087188A1

公开(公告)日：2019-03-21

申请号：US15709213

申请日：2017-09-19

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Tomasz Janczak ,  Travis Schluessler ,  Subramaniam Maiyuran

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/50 ,  G06T15/00

CPC classification number: G06F9/30123 ,  G06F9/3009 ,  G06F9/485 ,  G06F9/4881 ,  G06F9/505 ,  G06T15/005

Abstract: An apparatus to facilitate register allocation is disclosed. The apparatus includes an execution unit (EU) to execute processing threads. The EU includes a plurality of registers and register allocation logic to map the plurality of registers into logical register banks and allocate the processing threads to one or more of the logical register banks.

公开(公告)号：US20190035363A1

公开(公告)日：2019-01-31

申请号：US15858486

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  John Gierach ,  Tomer Bar-On ,  Devan Burke

IPC: G09G5/36 ,  G09G3/00 ,  G09G5/391 ,  G06T15/40 ,  G06T15/20 ,  G06T7/70 ,  G09G5/397

CPC classification number: G09G5/363 ,  G06F3/1446 ,  G06T1/20 ,  G06T1/60 ,  G06T3/0093 ,  G06T7/70 ,  G06T15/005 ,  G06T15/20 ,  G06T15/405 ,  G06T2210/08 ,  G06T2210/36 ,  G06T2210/52 ,  G09G3/003 ,  G09G5/001 ,  G09G5/377 ,  G09G5/391 ,  G09G5/397 ,  G09G2300/026 ,  G09G2320/0252 ,  G09G2330/023 ,  G09G2340/0407 ,  G09G2340/0428 ,  G09G2352/00 ,  G09G2354/00 ,  G09G2360/06 ,  G09G2360/08 ,  G09G2360/121 ,  G09G2360/122

Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.