公开(公告)号：JPH1197423A

公开(公告)日：1999-04-09

申请号：JP25683597

申请日：1997-09-22

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： KAMAKURA MASAARI ,  TOMONARI SHIGEAKI ,  OKA NAOMASA ,  NAKAMURA TAKURO ,  ISHIDA TAKUO ,  YOSHIDA HITOSHI

IPC: G01P15/12 ,  H01L21/302 ,  H01L21/3065 ,  H01L41/08 ,  H01L49/00

Abstract: PROBLEM TO BE SOLVED: To make it possible to suppress the formation of an inverted layer by automatic doping and diffusion of impurities into an epitaxial layer. SOLUTION: A field oxide film 2 is formed on an n-type silicon substrate 1. With photoresist which is patterned in the specified shape as a mask, an opening part 2a is formed by etching the field oxide film 2. The photoresist is removed. Then, with the field oxide film 2 wherein the opening part 2a is formed as a mask, p-type impurities are deposited. A p+ type embedded sacrifice layer 3 is formed by performing thermal diffusion in nitrogen atmosphere. Then, a silicon oxide film 4 is formed at the formed part of the opening part 2a by performing wet oxidation or pyrogenic oxidation. Then, the field oxide film 2 and the silicon oxide film 4 are completely etched and removed along the entire surface. An n-type epitaxial layer 5 is deposited on the formed side of the p+ type embedded sacrifice layer 3 of the silicon substrate 1. At this time, p-type impurities are diffused from the p+ type embedded sacrifice layer 3 through the interface with the silicon substrate 1, and a final p-type embedded sacrifice layer 6 is formed.

公开(公告)号：JPH10135266A

公开(公告)日：1998-05-22

申请号：JP28567696

申请日：1996-10-28

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： KUZUHARA KAZUNARI ,  TAKAMI SHIGENARI ,  OKA NAOMASA

IPC: H01L21/60 ,  H01L21/68

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and manufacture thereof, whereby the verification accuracy of the mounting position on a substrate is improved. SOLUTION: A semiconductor device 10, having a circuit pattern on the surface provides marks 4, formed on the back surface to clarify the relative pattern of the surface circuit pattern to specified part position. The marks 4 are formed on the back surface of the device 10, by using a double-sided mask aligner for masking, etching an oxide film 2 and nitride film or anisotropically etching silicon 1 itself.

公开(公告)号：JPH0982894A

公开(公告)日：1997-03-28

申请号：JP23738195

申请日：1995-09-14

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： AKAI SUMIO ,  OKA NAOMASA

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device possessed of a resistor which can be formed at a low cost on the same silicon substrate without an additional process besides a manufacturing process where CMOSs or EEPROMs are formed. SOLUTION: A first silicon oxide film 1 and a polycrystalline silicon film 2 are successively formed on the major surface of a P-type silicon substrate 10, and an H-shaped opening is provided to the films 1 and 2, and side wall films 5a and 5b are formed on the H-shaped opening. A resistor 11 formed of first N -type diffusion layer, a second N -type diffusion layer 12, and a contact layer 13 formed of N -type diffusion layer are formed inside the P-type silicon substrate 10 located below the opening H-shaped in horizontal cross section, and an Al-Si electrode is formed on the contact layer 13.

公开(公告)号：JPH06310591A

公开(公告)日：1994-11-04

申请号：JP9821693

申请日：1993-04-23

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L21/762 ,  H01L21/76 ,  H01L21/8238 ,  H01L27/092

Abstract: PURPOSE:To reduce leakage currents stationarily flowing from VDD to VSS while preventing a crosstalk between elements and an adverse effect by mutual noises by isolating a well region by a silicon oxide film from the surface and rear of a substrate. CONSTITUTION:An N-type silicon substrate 18 is thermally oxidized, and a silicon oxide film 19 is formed. The N-type silicon substrate 18 is etched in an anisotropic manner from the rear of a substrate, and a trench 18a is made to reach the rear of a silicon oxide thick film 22 formed onto the surface of the substrate. A silicon oxide film 24 is deposited on the rear of the N-type silicon substrate 18 through a CVD method as a protective film. Consequently, two electrically isolated regions are shaped onto the N-type silicon substrate 18 by the silicon oxide thick film 22 formed onto the surface of the substrate and the silicon oxide film 24 shaped into the trench 18a and brought into contact with the silicon oxide thick film 22. Accordingly, leakage currents between a D-type well region 29 and an N-type well region 30 can be reduced.

公开(公告)号：JPH05326973A

公开(公告)日：1993-12-10

申请号：JP12395192

申请日：1992-05-15

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To provide an EEPROM (nonvolatile electronic memory) easy to integrate highly and excellent in holding characteristics. CONSTITUTION:A nonvolatile electronic memory device 1 comprises a MOS transistor structure for floating gate type memory installed on a semiconductor substrate 2. A V-shape groove 3 whose inner surface is covered with a thermal oxide film 4 is formed in the semiconductor substrate 2. The MOS transistor structure for floating gate type memory is installed in the V-shape groove 3 so that a floating gate 5 is formed on the thermal oxide film 4 and the bottom of the V-shape groove 3. An impurity high concentration layer 24a for a MOS transistor on the surface of the semiconductor substrate 2 is used as a control gate, and a write/erase to the floating gate 5 is performed by energizing a power through the thermal oxide film 4.

公开(公告)号：JPH02215190A

公开(公告)日：1990-08-28

申请号：JP3593189

申请日：1989-02-15

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： SAIJO TAKASHI ,  OKA NAOMASA

IPC: H05K3/46

Abstract: PURPOSE:To prevent steps from occurring to another, wiring formed through the intermediary of an insulating film on a poly-Si wiring by a method wherein a non-wired section of a poly-Si film is selectively oxidized to be insulated and left, and a mono-oxidized section is made to serve as the poly-Si wiring. CONSTITUTION:A poly-Si film 12 is laminated on a thermal oxide film 11 formed on a semiconductor board 1. A patterned oxide film 13 and an Si nitride film 14 are provided onto the film 12. In succession, when the exposed surface of the film 12 is removed as thick as half or so through etching, the surface of the film 12 grows it be in the same state as the surface of a poly-Si film 12' is covered with a mask (film 14) of the same pattern as a specified pattern of a poly-Si wiring to be formed. In this state, when an oxidation treatment is executed, a non-masked film 12'' of the film 12, becomes insulated, and a part left non-oxidized is made to serve as an Si wiring 15. By this setup, an insulating film 16 formed in lamination does not rise due to the wiring 15, so that steps are prevented from occurring to a wiring formed on the film 16. Therefore, cracks and disconnection hardly happens to this wiring.

公开(公告)号：JPS635554A

公开(公告)日：1988-01-11

申请号：JP14900286

申请日：1986-06-25

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: PURPOSE:To enhance integration by a method wherein a trench is formed between two lateral channel regions, channel regions are formed on the sides of the trench, and a P-channel MOS transistor and N-channel MOS transistor are respectively provided with a plurality of channel regions. CONSTITUTION:Two lateral channels regions 2 and 4 are formed on a semiconductor substrate 1 and a trench 6 is provided between the two lateral channel regions 2 and 4, and channel regions 7 and 8 are formed on the sides of the trench 6, for a P-channel MOS transistor 3 and N-channel MOS transistor 5 to be provided respectively with a plurality of channel regions. In this way, a device of a certain current capacity may be constructed occupying an area smaller than in a conventional design, or a device of an enhanced current capacity may be constructed occupying the same area as in a conventional design, which enables integration to be enhanced.

公开(公告)号：JPS62172730A

公开(公告)日：1987-07-29

申请号：JP1498586

申请日：1986-01-27

Applicant: MATSUSHITA ELECTRIC WORKS LTD

Inventor： OKA NAOMASA

IPC: C23F1/00 ,  H01L21/306

Abstract: PURPOSE:To improve the precision of the pattern of the contact hole of the oxide film of the thinner one of Si oxide films by a method wherein, in case contact holes are formed in the Si oxide films having different film thicknesses by etching, a sidewall is formed by heat-treating a photo resist after the contact hole of the oxide film of the thinner one is opened and an etching is performed on the oxide film of the thickner one. CONSTITUTION:A pattern is formed on an oxide film 2 on the element forming region of an Si substrate and an Si oxide film 3 on the element isolation region of the Si substrate using a P-type photo resist 4 and the oxide films are etched using this photo resist 4 as a mask until a contact hole 7 of the Si oxide film 2 of the thinner one is opened. Then, if this Si substrate 1 is heated at a temperature of 180 deg.C for 30min, the photo resist 4 is softened and sags, whereby a sidewall 16 is formed on the inner peripheral surface of a side etching part 9. After such a heat treatment, the residue of the oxide film 3 of the thicker one is opened to form a contact hole 8. Thereby, in case the contact holes are simultaneously opened in the Si oxide films whose film thicknesses are different from each other, the precision of the pattern of the contact hole of the oxide film of the thinner one can be improved.

公开(公告)号：JP2006015439A

公开(公告)日：2006-01-19

申请号：JP2004194499

申请日：2004-06-30

Applicant: Matsushita Electric Works Ltd ,  松下電工株式会社

Inventor： YOSHIHARA TAKAAKI ,  OKA NAOMASA ,  OGIWARA ATSUSHI ,  USHIYAMA NAOKI ,  HARADA HIROSHI ,  KONO KIYOHIKO

IPC: B81C1/00

Abstract: PROBLEM TO BE SOLVED: To easily create a fine three-dimensional structure by suppressing the occurrence of a damaged part by side etching.
SOLUTION: This method of manufacturing a semiconductor structure has a patterning process for selectively eliminating a first substrate 11 from a first main surface of the first substrate 11 to form a plurality of groove parts different in depth, a substrate joining process for joining the first main surface to the main surface of a second substrate 12; and a back face etching process for uniformly eliminating the first substrate 11 from a second main surface 11b facing the first main surface, to leave only the projecting parts 14 between the grooves. Prior to the back face etching process, a level difference forming process is performed to form level differences 11c, 11d, 11e on the second main surface 11b by etching a shallow part shallower in the groove part depth than the other groove parts.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：通过抑制侧面蚀刻损坏的发生，容易地形成精细的三维结构。 解决方案：这种制造半导体结构的方法具有用于从第一基板11的第一主表面选择性地去除第一基板11以形成多个不同深度的槽部的图案化工艺，用于接合的基板接合工艺 第二基板12的主表面的第一主表面; 以及用于从面向第一主表面的第二主表面11b均匀地除去第一基板11以仅在凹槽之间仅留下突出部分14的背面蚀刻工艺。 在背面蚀刻工艺之前，通过蚀刻在凹槽部分深度比其他凹槽部分更浅的浅部分，执行电平差形成处理以形成第二主表面11b上的电平差11c，11d，11e。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005271187A

公开(公告)日：2005-10-06

申请号：JP2004092690

申请日：2004-03-26

Applicant: Matsushita Electric Works Ltd ,  松下電工株式会社

Inventor： OGIWARA ATSUSHI ,  HARADA HIROSHI ,  OKA NAOMASA ,  SUZUMURA MASAHIKO ,  NOGE HIROSHI ,  YOSHIHARA TAKAAKI ,  USHIYAMA NAOKI ,  KONO KIYOHIKO

IPC: G02B26/08 ,  B81B3/00

Abstract: PROBLEM TO BE SOLVED: To provide a micro-device and an optical switch which realize a latch function by a compact and simple operation. SOLUTION: The micro-device comprises: a movable plate 3; a flexible supporting arm 2 to support the movable plate 3; actuators (4, 6 and 7) to drive the movable plate 3 in the first direction and the second direction opposite to the first direction; a first member 5 connected to the movable plate 3, a second member 10 which is fitted to the first member 5 in a condition displaced in the first direction to hold the movable plate 3; and a flexible member 9 to displace the second member 10 in the direction substantially orthogonal to the first direction. The first member 5 and the second member 10 have tapered structures facing each other in the first and second directions. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供通过紧凑且简单的操作来实现闩锁功能的微型装置和光学开关。 解决方案：微型装置包括：可移动板3; 柔性支撑臂2，以支撑可动板3; 致动器（4,6和7），以沿着与第一方向相反的第一方向和第二方向驱动可动板3; 连接到可移动板3的第一构件5，以沿第一方向移位以保持可动板3的状态装配到第一构件5的第二构件10; 以及柔性构件9，以使第二构件10沿与第一方向大致正交的方向移位。 第一构件5和第二构件10具有在第一和第二方向上彼此面对的锥形结构。 版权所有（C）2006，JPO＆NCIPI