公开(公告)号：AU665718B2

公开(公告)日：1996-01-11

申请号：AU6734894

申请日：1994-07-08

Applicant: MOTOROLA INC

Inventor： BOCKELMAN DAVID E ,  STENGEL ROBERT E

IPC: H01P1/20 ,  H01L23/66 ,  H01P3/02 ,  H01P3/08 ,  H01R24/00 ,  H04B3/32 ,  H05K1/02 ,  H03F3/195 ,  H04B1/16 ,  H01L27/04

Abstract: The interconnection structure to reduce crosstalk in reentrant off-chip RF selectivity uses differential circuits (402,415), transmission lines (423,424) and off-chip filters (422) in a structure that balances the parasitic capacitances associated with all of the differential elements. The structure includes a substrate (409) with a differential generating circuit and a receiving circuit (415). Two differential transmission lines, each with constant characteristic impedance, and each with balanced capacitance to ground, are closely spaced for some distance and couple the circuits to closely spaced terminating pads (403). A ground plane (412) is shared under both transmission lines. A second substrate (408) has a reentrant RF path (406) with the first substrate and contains an RF function such as a filter or a delay line.

公开(公告)号：BR9403019A

公开(公告)日：1995-06-27

申请号：BR9403019

申请日：1994-08-30

Applicant: MOTOROLA INC

Inventor： BOCKELMAN DAVID E ,  STENGEL ROBERT E

IPC: H01P1/20 ,  H01L23/66 ,  H01P3/02 ,  H01P3/08 ,  H01R24/00 ,  H04B3/32 ,  H05K1/02 ,  H01L23/52 ,  H05K3/40

Abstract: The interconnection structure to reduce crosstalk in reentrant off-chip RF selectivity uses differential circuits (402,415), transmission lines (423,424) and off-chip filters (422) in a structure that balances the parasitic capacitances associated with all of the differential elements. The structure includes a substrate (409) with a differential generating circuit and a receiving circuit (415). Two differential transmission lines, each with constant characteristic impedance, and each with balanced capacitance to ground, are closely spaced for some distance and couple the circuits to closely spaced terminating pads (403). A ground plane (412) is shared under both transmission lines. A second substrate (408) has a reentrant RF path (406) with the first substrate and contains an RF function such as a filter or a delay line.

公开(公告)号：EP1886405A4

公开(公告)日：2009-12-02

申请号：EP06751656

申请日：2006-04-27

Applicant: MOTOROLA INC

Inventor： THOMPSON BRUCE M ,  STENGEL ROBERT E

IPC: H03F3/60

CPC classification number: H03F3/605

公开(公告)号：EP1444783A4

公开(公告)日：2005-02-02

申请号：EP02773869

申请日：2002-10-23

Applicant: MOTOROLA INC

Inventor： JUAN JUI-KUO ,  STENGEL ROBERT E ,  MARTIN FREDERICK L ,  BOCKELMAN DAVID E

IPC: H03L7/07 ,  H03L7/081 ,  H03L7/14 ,  H03L7/16 ,  H03H11/26

CPC classification number: H03L7/16 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/14 ,  H03L2207/08

Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.

公开(公告)号：CA2582350C

公开(公告)日：2013-05-14

申请号：CA2582350

申请日：2005-09-14

Applicant: MOTOROLA INC

Inventor： GRADISHAR THOMAS L ,  STENGEL ROBERT E

IPC: H03L1/00 ,  H03K3/011 ,  H03K5/14 ,  H03L7/06 ,  H03M1/08 ,  H04B15/00

Abstract: A direct digital synthesizer (DDS) (300) that uses a system for reducing spurious emissions in a digital-to-time converter (DTC) (317). The DDS (300) includes one or more dither sources (307) and a random access memory (RAM) (305). The RAM (305) utilizes a look-up table for storing delay error values by using an output of the look-up table which is combined with the dither source (307) to compensate unequal unit delay values in the DTC (317).

公开(公告)号：AU2006246355B2

公开(公告)日：2009-08-13

申请号：AU2006246355

申请日：2006-04-27

Applicant: MOTOROLA INC

Inventor： THOMPSON BRUCE M ,  STENGEL ROBERT E

IPC: H03F3/60

Abstract: A system and a method for providing an input to a distributed power amplifying system are provided. In an embodiment, a distributed power amplifying system includes a plurality of amplifying sections ( 102, 104, 106 , and 108 ) and a plurality of drivers ( 110, 112, 114 , and 116 ). Each of the plurality of drivers receives a common transmit signal ( 118 ) and an individual control signal ( 120, 122, 124 , and 126 ). Each of the plurality of drivers independently preconditions the common transmit signal, to provide a transmit output signal ( 128, 130, 132 , and 134 ) to each of the plurality of amplifying sections. The common transmit signal provided to each of the plurality of drivers is preconditioned, based on the individual control signal.

公开(公告)号：CA2629541A1

公开(公告)日：2007-05-31

申请号：CA2629541

申请日：2006-10-09

Applicant: MOTOROLA INC

Inventor： STENGEL ROBERT E ,  THOMPSON BRUCE M ,  OOI LENG H

IPC: G06F15/00

Abstract: A vector signal processor (80) can include a digital to time converter (DTC), an RF memory (RFM) or an electronically tunable transmission line (ETTL) (82), a mixer, or other phase shifter (70) for receiving an output of the DTC or the ETTL, and a controller for selectively controlling the harmonic processing of the DTC, RFM or the ETTL and the phase processing of the mixer. The vector signal processor can uncouple a relative phase of a fundamental signal with respect to harmonics of the fundamental signal. The vector signal processor uses selective phase processing of the fundamental signal and related harmonic components. In a specific embodiment, the vector signal processor cancels harmonics of the fundamental signal and more specifically can cancel a third harmonic of the fundamental signal.

公开(公告)号：MY115426A

公开(公告)日：2003-06-30

申请号：MYPI9402249

申请日：1994-08-26

Applicant: MOTOROLA INC

Inventor： BOCKELMAN DAVID E ,  STENGEL ROBERT E

IPC: H01P1/20 ,  H01P3/08 ,  H01L23/66 ,  H01P3/02 ,  H01R24/00 ,  H04B3/32 ,  H05K1/02

Abstract: TO REDUCE CROSSTALK IN REENTRANT OFF-CHIP RF SELECTIVITY,DIFFERENTIAL CIRCUITS (402,415),TRANSMISSION LINES (423,424), AND OFF-CHIP FILTERS (422) ARE USED IN A STRUCTURE THAT BALANCES THE PARASITIC CAPACITANCES ASSOCIATED WITH ALL OF THE DIFFERENTIAL ELEMENTS.THE STRUCTURE INCLUDES A SUBSTRATE (409) WITH A DIFFERENTIAL GENERATING CIRCUIT (402) AND A RECEIVING CIRCUIT (415).TWO DIFFERENTIAL TRANSMISSION LINES (423,424),EACH WITH CONSTANT CHARACTERISTIC IMPEDANCE, AND EACH WITH BALANCED CAPACITANCE TO GROUND,BOTH BEING CLOSELY SPACED FOR SOME DISTANCE,COUPLE THE CIRCUIT (402,415) TO CLOSELY SPACED TERMINATING PADS (403). A GROUND PLANE (412) IS SHARED UNDER BOTH TRANSMISSION LINES (423,424). A SECOND SUBSTRATE (408) HAVING A REENTRANT RF PATH (406) WITH THE FIRST SUBSTRATE (409) CONTAINS AN RF FUNCTION SUCH AS A FILTER OR A DELAY LINE.FIG. 4

公开(公告)号：AU2002337964A1

公开(公告)日：2003-05-19

申请号：AU2002337964

申请日：2002-10-23

Applicant: MOTOROLA INC

Inventor： STENGEL ROBERT E ,  JUAN JUI-KUO ,  BOCKELMAN DAVID E ,  MARTIN FREDERICK L

IPC: H03L7/07 ,  H03L7/081 ,  H03L7/14 ,  H03L7/16 ,  H03D3/24

Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element ( 24 ) and one or more secondary delay elements ( 162 . . . 164, 270, 310 ). In one embodiment, a main delay line ( 24 ) is used to coarsely select a frequency output while a secondary delay element ( 162 . . . 164, 270, 310 ), either passive or active, is used to increase the resolution of the primary delay line ( 24 ). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line ( 24 ) as a driving signal for the passive secondary delay element ( 310 ) to provide the coarse adjustment and selecting an output from the secondary delay element ( 310 ) to provide the fine selection.

公开(公告)号：AU2002332403A1

公开(公告)日：2003-01-21

申请号：AU2002332403

申请日：2002-07-02

Applicant: MOTOROLA INC

Inventor： MARTIN FREDERICK L ,  STENGEL ROBERT E ,  BAUTISTA EDWIN E

IPC: H04L27/20 ,  H04L27/36

Abstract: Phase shift key modulators ( 100, 500, 1000, 1400, 1700 ) are provided in which a multiphase signal source ( 108, 1402, 1406 - 1412,1702 ) is used to generate a plurality of phases of a carrier signal. A selector ( 110 ) is used to select one phase or a sequence of phases of the carrier signal to represent each bit pattern that is received from a binary data source ( 102, 1422 ). The multiphase signal source preferably comprises a multiphase oscillator that includes a phase locked ring of variable propagation delay inverters ( 202 ). Preferably, a phase sequencer ( 502 ) is used to select a monotonic sequence of phases to represent each bit pattern. Preferably two phase selectors ( 110, 1004 ) are used to simultaneously select two phases of carrier signal, and a phase interpolator ( 1106 ) is used to generate a sequence of phases from the two phases selected by the two phase selectors ( 110, 1004 ).